The ever-increasing complexity of design specifications for processors and intellectual property (IP) presents a formidable challenge for early bug detection in the modern IC design cycle. The recent advancements in hardware fuzzing have proven effective in the design verification of complex hardware designs. The modern IC design flow involves incremental updates and modifications to the hardware designs, necessitating rigorous verification and extending the overall verification period. A major challenge lies in generating high-quality seeds that maximize coverage and verification efficiency. While Coverage-Guided Fuzzing (CGF) enhances overall exploration, it lacks precision when targeting specific sites. DirectFuzz addresses this with directed test generation but suffers from key limitations, including limited HDL support, abstraction mismatches, and poor scalability for large target regions. In this work, to overcome these challenges, we propose TargetFuzz, a Directed Graybox Fuzzing (DGF) framework that integrates SAT (Boolean satisfiability) engines for precise and scalable seed generation. Our experimental results demonstrate its capability to effectively scale 30x greater in terms of handling target sites, achieving 100% state coverage and $1.5 x$ faster in terms of site coverage, and show 90x improvement in target state coverage compared to Coverage-Guided Fuzzing, demonstrating its potential to advance the state-of-the-art in directed hardware fuzzing.

The adoption of Large Language Models (LLMs) in Electronic Design Automation (EDA) has demonstrated significant potential for automating Register-Transfer Level (RTL) generation and verification; however, conventional prompt-based or fine-tuned approaches often fail to produce structurally consistent RTL and meaningful assertions for complex designs. We present VeriRAG, a hybrid retrieval-augmented generation framework that combines hardware-specific knowledge graphs with semantic vector embeddings. This hybrid retrieval strategy provides both symbolic structural context and semantic content, enabling the LLM to generate synthesizable Verilog and valid SystemVerilog Assertions (SVAs) without relying on rigid manual intervention or costly retraining. Experimental results across a diverse set of representative designs show that VeriRAG achieves up to 97% syntax correctness and 100% functional success for RTL generation, with SVAs reaching 100% syntax validity and 95% Formal Property Verification (FPV) pass rates using standard EDA tools. These results highlight the potential of combining symbolic knowledge graphs with retrieval-augmented generation for scalable, verifiable hardware design workflows.

Hardware fuzzing is critical for uncovering vulnerabilities in modern integrated circuits by systematically exploring input spaces. A major challenge lies in generating high-quality seeds that maximize coverage and verification efficiency. While Coverage-Guided Fuzzing (CGF) enhances overall exploration, it lacks precision when targeting specific submodules. DirectFuzz addresses this with directed test generation but suffers from key limitations, including limited HDL support, abstraction mismatches, and poor scalability for large target regions. In this work, to overcome these challenges, we propose PROFUZZ, a Directed Graybox Fuzzing (DGF) framework that integrates Automatic Test Pattern Generation (ATPG) for precise and scalable seed generation. By leveraging ATPG’s structural analysis capabilities, PROFUZZ improves coverage effectiveness and supports large-scale hardware designs. Experimental results show that PROFUZZ outperforms DirectFuzz with 30× greater scalability in terms of handling target sites, 11.66% higher coverage, and 2.76× faster execution, demonstrating its potential to advance the state-of-the-art in directed hardware fuzzing.

Hardware Security is at stake driven by the growing complexity and integration of processors, SoCs, and diverse third-party intellectual property (IP) hardware, all geared toward delivering advanced solutions. To preserve the system integrity and mitigate the post-production re-engineering costs, the Design Verification (DV) community employs dynamic and formal verification strategies. However, with the ever-increasing complexity of modern processors, these techniques fall in short of scalability and increased verification time. Recently, hardware fuzzing inspired by software testing has been navigating uncharted territories in hardware bug detection capabilities. Multiple hardware fuzzing techniques have been recently introduced that either utilize the hardware design in its inherent form for fuzzing or convert the hardware into software models and perform fuzzing to detect bugs. However, the existing techniques claim to be a silver bullet in their way, we provide some critical insights on these techniques by reviewing the fundamental principles of hardware fuzzing frameworks, the methodologies involved, and the diverse hardware designs in which they can be employed. Furthermore, we discuss the challenges and limitations of the fuzzing framework. We also present feasible future research directions based on our observations and insights.

The increasing complexity and integration of diverse components in modern System-on-Chip (SoC) designs make them susceptible to a range of attacks. Unfortunately, a substantial disjunction persists between the sophisticated architectures of the SoCs and Design Verification (DV) techniques to detect such vulnerabilities. Recently, Hardware fuzzing, inspired by software testing, has been gaining attention for its efficient bug-detection capabilities in SoC designs. Coverage metrics serve as a pivotal tool in assessing the efficacy of fuzzing techniques by gauging the extent to which the Design Under Test (DUT) design space is explored during the verification process. This paper endeavors to delve into various hardware coverage metrics, encompassing branch, statement, Finite State Machine (FSM), line, and expression coverage, in order to elucidate both the merits and demerits of existing hardware fuzzing methodologies. Furthermore, it seeks to explore how these coverage metrics can be harnessed to bolster the efficacy of hardware fuzzing, thereby augmenting bug detection rates and streamlining testing endeavors. This work provides an analysis on different coverage metrics that could be utilized and the impact of it on the overall design coverage for various IP blocks and CPU designs.

Reconfigurable nanotechnologies such as Silicon Nanowire Field Effect Transistors (FETs) serve as a promising technology that not only facilitates lower power consumption but also supports multi-functionality through reconfigurability. It enables reconfigurability and supports multiple functionalities per computational unit. These features motivate us to design a novel state-of-the-art energy-efficient hardware accelerator for implementing memory-intensive applications including convolutional neural networks (CNNs) and deep neural networks (DNNs). To accelerate the computations, we design Multiply and Accumulate (MAC) units to perform the computations. For the design of MACs, we employ Silicon nanowire reconfigurable FETs (RFETs). The use of RFETs leads to nearly 70% power reduction compared to the traditional CMOS implementation and also reduced latency in performing the computations. Further to optimize the overheads and improve memory efficiency, we introduce a novel approximation technique for RFETs. The RFET-based approximate adders lead to reduced power, area, and delay while having a minimal impact on the accuracy of the DNN/CNN. In addition, we carry out a detailed study of varied combinations of architectures involving CMOS, RFETs, accurate adders, and approximate adders to demonstrate the benefits of the proposed RFET-based approximate acclerator. The proposed RFET-based accelerator achieves an accuracy of 94% on MNIST datasets with 93% and 73%reduction in the area, power and delay metrics respectively compared to the state-of-the-art hardware accelerator architectures.