This paper presents an effective digital calibration method based on Volterra neural network (VNN) for pipeline analog-to-digital converters (ADCs). Typically, the nonideality of pipelined ADCs results in dynamic nonlinear systems that are difficult to comprehensively calibrate. The proposed approach combines the strong nonlinear modeling capabilities of Volterra series with the adaptability of neural networks to accurately compensate for nonlinear distortions in pipeline ADCs. The effectiveness of VNN-based calibration is verified in MATLAB and ZYNQ-7000 FPGA. A 625-MS/s 12-bit pipeline ADC in 28 nm CMOS process is presented to verify the proposed calibration technique. The experimental results show that owing to the proposed powerful calibrator, the SFDR and SNDR achieve 79.8 dB and 60.7 dB at low frequencies, 74.3 dB and 59.1 dB at high frequencies, respectively.

This brief presents a digital calibration for pipelined analog-to-digital converters (ADCs) utilizing the cascaded nonlinearity correction (CNC) method. By cascading three correction layers for compensating nonlinearities in different parts of pipelined ADC, it comprehensively calibrates distortion in both ADC front end and back end with a low hardware cost. In addition, this work employs a discriminative fine-tuning least-mean-square (DFT-LMS) algorithm with varying step sizes for different layers, thereby improving both the convergence speed and the accuracy. An 800-MS/s, 12-bit ring amplifier-based pipelined ADC is presented to verify the proposed calibration technique. With calibration, the SFDR has a 26.7-dB improvement at low frequency and 23.6-dB improvement at Nyquist frequency, resulting in over 6-dB improvement compared with prior-art calibration techniques. The calibration algorithm has been verified on a TSMC 28-nm CMOS process. The experimental results show that the proposed ADC calibrator has an area of$6592~\mu $m2 and consumes 5.31 mW at 800-MHz clock rate.

In this paper, a fully digital calibration based on sinusoidal fitting (sine-fit) is proposed to overcome the difficulty of signal fitting in hardware implementation. The two-step frequency detection, grouping and recursive sine-fit method are proposed to address the trade-off between frequency estimation accuracy and hardware overhead. The simulation results in MATLAB and FPGA-based hardware verification are employed to demonstrate the performance and hardware overhead. A 400-MS/s 12-bit voltage-time hybrid pipeline ADC in a 28 nm CMOS process is presented to verify the proposed calibration technique, the simulation results show that the Nyquist-rate SFDR and SNDR are improved by 12.2 dB and 11.4 dB, respectively.

This paper presents a 400-MS/s 12-bit voltage-time hybrid pipeline ADC in a 28 nm CMOS process. The first stage is an asynchronous SAR ADC resolving 6 bits, and the second stage is a time-domain ADC composed of a VTC and a 7-bit SAR TDC (with 1-bit redundancy). To speed up the time domain operation, a ping-pong switching technique is used in the second stage. Besides, a common mode VTC is adopted to improve the linearity during the voltage-to-time conversion. A non-binary SAR TDC is also designed to tolerate the MSBs decision errors in the time-domain quantization. Furthermore, a LMS-based background calibration is performed to correct the capacitor mismatch error, interstage gain error, and bit-weight in the SAR TDC. The simulation results show that this design achieves a SNDR of 63.3 dB and a SFDR of 79.1 dB at Nyquist input. The power consumption is 9.6 mW with a supply of 0.9V, showing a FoM of 20.1 fJ/conversion-step.