Liting Tang

dblp:353/7830 · DBLP profile ↗
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2ranked-venue papers
0as first author
2since 2021 · last 2025
0009-0007-6708-8296ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 100%
Software engineering, system software, and programming languages
1 paper
Compilers and program optimization · 100%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
cache
0.912025
DTAP: Accelerating Strongly-Typed Programs with Data Type-Aware Hardware Prefetching · ACM Trans. Archit. Code Optim. 2025
Memory systems › cache
cache miss reduction
0.912025
DTAP: Accelerating Strongly-Typed Programs with Data Type-Aware Hardware Prefetching · ACM Trans. Archit. Code Optim. 2025
Memory systems › cache › prefetching
hardware prefetching
0.912025
DTAP: Accelerating Strongly-Typed Programs with Data Type-Aware Hardware Prefetching · ACM Trans. Archit. Code Optim. 2025

Methods — techniques the papers use, named apart from their topics

software-hardware co-design · 1.7
YearPublicationVenuePosition
2025 DTAP: Accelerating Strongly-Typed Programs with Data Type-Aware Hardware Prefetching
abstract
Queries on linked data structures, such as trees and graphs, often suffer from frequent cache misses and significant performance loss due to dependent and random pointer-chasing memory accesses. In this article, we propose a software-hardware co-designed solution for accelerating linked data structures implemented in strongly typed languages. The solution incorporates a compiler extension and a hardware prefetcher. The compiler extension extracts type information from the code, annotates each load instruction, and forwards the type information to the hardware prefetcher. The prefetcher leverages the type information to fetch the referred objects and identify the associated pointers in advance. By doing so, the program can find these objects in the cache when it follows the prefetched pointers, thus minimizing cache misses. In the evaluation, the proposed solution achieves an average speedup of 1.37× over a set of memory-intensive benchmarks.
Yingshuai Dong, Chencheng Ye 0001, Haikun Liu, Liting Tang, Xiaofei Liao, Hai Jin 0001, Yanjiang Li
ACM Trans. Archit. Code Optim.4
2023 VIDGCN: Embracing input data diversity with a configurable graph convolutional network accelerator
Tingting Pan, Dong Chen 0015, Chencheng Ye 0001, Haikun Liu, Liting Tang, Xiaofei Liao, Hai Jin 0001
J. Syst. Archit.6