The hardware convergence of Artificial Neural Networks (ANNs) and Spiking Neural Networks (SNNs) is hindered by conflicting computational paradigms: dense tensor parallelism versus asynchronous sparse dynamics. Existing unifications typically rely on inefficient spatial partitioning or mode-reconfigurable datapaths, limiting the flexibility needed by heterogeneous ANN-SNN hybrid models requiring frequent cross-domain interaction. To resolve this, we present NeuroUNI, a unified event-driven multi-core architecture. Unlike partitioned designs, NeuroUNI unifies computation at the primitive level using a novel Five-Tuple Event Model, abstracting both continuous activations and discrete spikes to naturally leverage dynamic sparsity. The architecture features a co-optimized hierarchical Macro-Micro-$\mu $OP ISA, a superscalar SIMD-based microarchitecture, and a decentralized multi-core synchronization protocol. Validated in TSMC 28nm technology via post-synthesis simulation and on a Xilinx VCU129 FPGA prototype, NeuroUNI demonstrates competitive cross-paradigm efficiency. It achieves$35.0\times $and$1.21\times $the ANN energy efficiency of the NVIDIA V100 and EyerissV2, respectively, while delivering$5.7\times $the SNN throughput of TrueNorth. In a unified mapless navigation workload, NeuroUNI attains 422.6 GOPS/W (ANN) and 190.8GSOPS/W (SNN), outperforming Loihi 1 with$56.7\times $the throughput and$3.85\times $the energy efficiency, proving the viability of a primitive/ISA-level unified silicon substrate.

By simulating the neurodynamics of biological brains, Spiking Neural Networks (SNNs) leverage sparse spike signal, eliminating the continuous multiply-accumulate operations of traditional Artificial Neural Networks (ANNs). Event-driven SNN processing offers significant advantages in energy efficiency and latency, making it ideal to be deployed on low-end processors. Spiking Convolutional Neural Networks (SC-NNs), which incorporate event-based processing, are increasingly employed for their power efficiency and ability to process spatio-temporal information. Unlike fully-connected networks, which rely on regular vector calculations, convolution operations present challenges for event-driven computation due to their sliding window nature.In this work, we deployed a compact 7-layer SCNN on the ARM Cortex-A9 core of PYNQ Z2 development board, using event-based acceleration. By optimizing data storage and processing sequences, we achieved efficient low-cost deployment. Offline training on the DVS128-Gesture dataset for an object recognition task yielded an accuracy of 93.40%. Following low-precision quantization and deployment, the model maintained a considerable accuracy of 92.36%. Compared to traditional periodic computation, event-based convolution processing achieved a 12.87× speedup. Furthermore, by exploiting the parallelism of feature map data storage along the channel dimension and ARM NEON instruction set, we gained an additional 2.97× speedup.

This paper introduce SPRCpl, an efficient compiler/toolkit for deploying Spiking Neural Network (SNN) models on multi-core neuromorphic chips. It uses "pilot running" to optimize the deployment process. It includes a front-end compiler, synapse pruning and regeneration optimizer, and a mapping tool. SPRCpl proposes a synapse pruning scheme based on spike firing statistics obtained through pilot running, dynamically reducing model size. It also presents a mapping scheme that minimizes strikes within and between clusters using spike firing statistics and multi-objective optimization. Experimental results demonstrate SPRCpl’s effectiveness in maintaining model accuracy during pruning and outperforming SpiNeMap in terms of communication count, execution time, and memory usage. It achieves lower latency, reduced power consumption, and higher throughput, making it a promising tool for SNN model deployment on multi-core neuromorphic chips.

Multi-core neuromorphic hardware for spiking neural networks (SNNs) has garnered considerable attention due to its biological plausibility and energy efficiency. However, the performance of SNN applications on such hardware is constrained by the rigid architecture and interconnection among neuron cores. To enable early-stage evaluation of SNN performance on multi-core neuromorphic hardware, we introduce an accurate and scalable simulator, SpikeNC. We present the entire workflow, ranging from SNN model training to simulation, providing comprehensive insights into both model and Network-on-Chip (NoC) related statistics. Moreover, we identify a considerable amount of time wastage in the widely adopted tick-based synchronous scheme. A three-stage agent-based asynchronous scheme is proposed for fast simulation. We evaluate the performance of deep spiking neural networks (DSNNs) with various scales trained on spike-converted datasets using SpikeNC. The results demonstrate that SpikeNC achieves precise and scalable simulation for SNNs on multi-core neuromorphic hardware. Additionally, the proposed asynchronous scheme significantly reduces the simulation cycles and absolute simulation time by approximately 63 % and 56 % respectively, compared to the synchronous scheme. We also delve into the trade-offs between different design parameters and explore the influence of mapping schemes utilizing SpikeNC.