Compiler mechanisms for Software-Implemented Hardware Fault Tolerance (SIHFT) offer a cost-effective solution for reliability, paving the way towards the adoption of Commercial Off-The-Shelf (COTS) components in safety-critical environments. However, default compiler optimizations can remove the SIHFT-induced redundancy and checks. For this reason, the use of compiler optimizations was discouraged in the literature. This article presents a comprehensive study of the reliability degradation introduced by LLVM’s O2 optimization pipeline when using a state-of-the-art SIHFT tool. We quantify, via RTL fault injection, the impact of O2 at different optimization stages, which identified a data corruption rate increase by up to $48 \times$. We also propose a static exploration methodology to identify the LLVM passes that harm the reliability. Then, we remove these harmful passes from the optimization pipeline, demonstrating how to tune optimization pipelines to make SIHFT successful even in the presence of compiler optimizations.

With version 17, LLVM finalized the transition to opaque pointer types, eliminating explicit pointee‑type information from the Intermediate Representation (IR). Thus, starting from LLVM 17, each pointer type is represented in IR by the unique type ptr. Despite eliminating redundant pointer bitcasts and consequently reducing IR size and compile time, this change disrupts analyses that have reason to rely on pointee-type information, forcing existing compiler projects to depend on outdated LLVM versions. This information can in fact be insightful in fields like approximate computing, where the compiler can apply non-conservative optimizations, or in passes that require it to make analyses and transformations that do not impact the correctness of the program. To address this problem, we present a new Type Deduction Analysis pass that reconstructs transparent pointer types directly from opaque‑pointer IR. Moreover, we illustrate two different case-studies on existing LLVM projects, namely TAFFO and ASPIS, that demonstrate the need for pointee-type information in LLVM compilers.

Compiler-based fault tolerance is a cost-effective and flexible family of solutions that transparently improves software reliability. This paper evaluates a compiler tool for fault detection via laser injection and α-particle exposure. A novel memory allocation strategy is proposed to mitigate the effects of multi-bit upsets. We integrated the detection mechanism with a recovery solution based on mixed-criticality scheduling. The results demonstrate the error detection and recovery capabilities in realistic scenarios: reducing undetected errors, enhancing system reliability, and advancing software-implemented fault tolerance.

Modern HPC systems must be designed considering different parameters, which include cost, performance, and throughput, as well as non-functional properties, such as power/energy consumption and reliability. This paper describes the work performed and the results achieved by the partners of the Italian National Research Center for HPC, Big Data and Quantum Computing in the frame of the sub-project dealing with Future HPC architectures and solutions. The work in this subproject focused on advanced design and monitoring techniques for devising energy- and power-efficient, reliable parallel architectures based on open standards (e.g., RISC-V) and design space exploration techniques and tools. This paper provides a summary of the achieved results and developed products stemming from the activities of the different partners.

ASTRAEUS project aims to improve the use of Commercial-Off-The-Shelf (COTS) devices in space telecommunication applications. The goal is to develop specialized radiation mitigation techniques for both hardware and software components with a special focus on the latter. The aim is to demonstrate the feasibility and reliability of these techniques, enabling their future use in telecommunication payload processing units. The SIHFT (Software Implemented Hardware Fault Tolerance) approach will be enforced, where some proper modification to a conventional compilation toolchain, will make possible the identification of temporary fault and the adoption of fault tolerant solutions. The successful implementation of this project will de-risk the use of software-based radiation mitigation techniques and foster the adoption of high-performance while cost-effective COTS electronics in space applications.

Software-Implemented Hardware Fault Tolerance (SIHFT) is advantageous in critical systems where hardware solutions cannot be used due to competing non-functional constraints. Recent works have focused on developing compiler-based protection mechanisms, relying on debuggers and other software mechanisms to introduce single event upsets. In this work, we test a compiler-based technique using physical radiation testing methods, including laser fault injection and alpha-particle exposure. During this evaluation, we identified previously unknown issues that required further development, including a novel memory allocation strategy for improved reliability. Furthermore, we integrated this fault detection solution with a hard real-time recovery mechanism that exploits mixed-criticality scheduling to demonstrate the overall system recovery capabilities. The results show the effectiveness of the proposed approach in detecting faults even under real-world radiation conditions, representing an important step toward the maturity of SIHFT techniques.

The problem of compiler optimization selection and ordering, known in the literature as compiler autotuning, has been tackled many times for average-case execution time reduction. Optimizing the WCET is becoming a prominent problem for modern hard real-time systems, where the difficulties in accurate WCET estimation hinder the full exploitation of computing platform capabilities. In this article, we propose a novel methodology and a tool based on LLVM for iterative WCET-driven compiler autotuning, which is the first strategy to operate at function-level granularity and to consider not only the selection of optimization passes, but also their ordering. Our findings show that standard optimization levels$\mathrm{O} 0, \mathrm{O} 1, \mathrm{O} 2$, and O 3 are suboptimal when targeting the WCET, and that a per-function selection and ordering of the transformations is necessary. Experimental results show that our approach outperforms the standard optimizations and opens up new directions for future research.

Software-Implemented Hardware Fault Tolerance (SIHFT) is a modern approach for tackling random hardware faults of dependable systems employing solely software solutions. This work extends an automatic compiler-based SIHFT hardening tool called ASPIS, enhancing it with novel protection mechanisms and overhead-reduction techniques, also providing an extensive analysis of its compliance with the non-trivial workload of the open-source Real-Time Operating System FreeRTOS. A thorough experimental fault-injection campaign on an STM32 board shows how the system achieves remarkably high tolerance to single-event upsets and a comparison between the SIHFT mechanisms implemented summarises the tradeoff between the overhead introduced and the detection capabilities of the various solutions.

Random hardware faults are a major concern for critical systems, especially when they are employed in high-radiation environments such as aerospace applications. While specialised hardware already exists for implementing fault tolerance, software solutions, named Software-Implemented Hardware Fault Tolerance (SIHFT), offer higher flexibility at a lower cost. This work describes a compiler-based approach for inserting instruction-level fault detection mechanisms in both the application code and the operating system. An experimental evaluation on a STM32 board running FreeRTOS shows the effectiveness of the proposed approach in detecting faults.