3D ICs extend integration freedom beyond post-Moore limits and can improve performance. Yet, existing true-3D placers remain primarily wirelength-driven, and partition-based 3D flows struggle to incorporate timing during design-space exploration. Prior 2D timing-driven approaches often rely on RSMT-based routing lookahead, which is unstable under z-moves and lacks a smooth objective for gradient-based optimization; simple net weighting further fails to capture path-level timing. We present IDDA-3D, the first timing-driven placement framework for face-to-face (F2F) bonded 3D ICs. IDDA-3D introduces a quadratic RC formulation that models intra-/inter-die driver-sink delay as a differentiable timing cost for analytical placement. The RC parameters are derived directly from the technology library, ensuring that the model reflects physical delay accurately and remains applicable across diverse technology nodes without manual tuning. To handle the discrete nature of die assignment, we employ a finite-difference approximation (FDA)-based gradient computation with preconditioning, which integrates seamlessly with the analytical placement engine. Experimental results show that IDDA-3D improves total negative slack (TNS) by up to 44% and worst negative slack (WNS) by 22%, while maintaining competitive wirelength and runtime compared with state-of-the-art true-3D placers.

Due to the rapid expansion of printed circuit board (PCB) designs, accompanied by diverse design rules and specific constraints, there has been a substantial increase in manual design engineering efforts. To address this challenge, industries are seeking productivity improvements through automated placement techniques. However, existing placers primarily target VLSI placement and do not align well with PCBs’ unique characteristics. This mismatch arises from both the customization of PCBs and the complexity of the problem, which involves considering various constraints such as priorities, irregularities, and alignment. This paper introduces HiePlace, an efficient mathematical programming (MP)-based placement framework designed explicitly for PCBs. It aims to address the diverse constraints and achieve better performance. To address the issue of time-consuming computation in the direct MP-based algorithm, we present two innovative acceleration techniques: (1) In the initial stage, we introduce a dynamic programming approach to prioritize the placement of core components. This technique effectively reduces the solution space and enhances the overall placement quality. (2) Additionally, we propose a relaxation algorithm to minimize the number of boolean variables and further narrow down the solution space. This approach enables more efficient placement results by considering the problems specific constraints. Experimental results show that the proposed framework produces 7.7× speed up and 66% cost reduction.

Interposer-based packaging has emerged as a pivotal technology for integrating advanced logic and memory chiplets in artificial intelligence (AI) and high-performance computing (HPC) systems. To accommodate growing system complexity, ultra-large wafer-scale integration employs expanded silicon interposers to support more chiplets. However, manufacturing such interposers exceeds the limits of single-mask lithography, requiring mask stitching, a technique that introduces unique physical design constraints and structural discontinuities. Additionally, thermo-mechanical stress, particularly near through-silicon vias (TSVs) and stitching regions, poses critical reliability challenges that conventional floorplanning methods fail to address. This paper presents MMPack, a hierarchical analytical framework for multi-mask chiplet-package co-design. Our approach integrates three key innovations: (1) a performance-driven partitioning algorithm that minimizes inter-chiplet and inter-mask communication overhead; (2) a stitching-aware hierarchical floorplanning strategy based on alternating optimization to address mask boundary constraints; and (3) a stress-aware post-processing step that employs an analytical model to reduce critical stress concentrations while preserving floorplanning quality. Experimental results demonstrate that MMPack significantly enhances both architectural performance and mechanical reliability while maintaining efficient layout and runtime scalability. These results highlight the practicality of our framework for enabling robust, high-performance designs in next-generation wafer-scale integration systems.

A chiplet is an integrated circuit (IC) that encompasses a well-defined subset of an overall systems functionality. In contrast to traditional monolithic system-on-chips (SoCs), chipletbased architecture can reduce costs and increase reusability, representing a promising avenue for continuing Moore’s Law. Despite the advantages of multi-chiplet architectures, floorplan design in a chiplet-based architecture has received limited attention. Conflicts between cost and performance necessitate a trade-off in chiplet floorplan design since additional latency introduced by advanced packaging can decrease performance. Consequently, balancing performance, cost, area, and reliability is of paramount importance. To address this challenge, we propose Floorplet (Floorplan chiplet), a framework comprising simulation tools for performance reporting and comprehensive models for cost and reliability optimization. Our framework employs the open-source Gem5 simulator to establish the relationship between performance and floorplan for the first time, guiding the floorplan optimization of multi-chiplet architecture. The experimental results show that our method decreases inter-chiplet communication costs by 24.81%.