Driven by the swift expansion of energy-demanding Internet of Things devices, on-chip SRAM is undergoing a significant evolution to attain reduced power usage. This shift ushers in a new era of self-sufficient and energy-efficient technology. This article proposes a novel 9-transistor Write Assist Read Decoupled (WARD) SRAM bitcell designed to achieve significant reductions in write latency. The design incorporates a low threshold (V TH ) write access transistor and leverages virtual ground (VGND) assist for low voltage operation at 32 nm CMOS technology node. It demonstrates notable improvements in write delay over conventional SRAM bitcells. At an operating voltage of 0.6 V, the WARD 9T cell offers reduced write “1” delay and write “0” delay by 3.18x/3.09x/2.42x/2.11x and 1.5x/1.475x/1.4x/1.37x/1.12x/1.118x compared to 9T half select free write assist (HFWA)/10T/9T single bitline (SB)/7T single-ended (SE) and 11T/9T HFWA/10T/9T transmission based read decoupled (TRD)/9T SB/7T SE cell SRAM bitcells, respectively. Additionally, WARD 9T cell demonstrates a substantial reduction in read delay by 1.56x/1.56x/8.44x compared to 11T/8T positive feedback controlled (PFC)/9T SB SRAM bitcells, respectively. To validate its performance, the WARD 9T SRAM bitcell undergoes evaluation across various supply voltages, process corners at varied temperature ranges, considering the impact of voltage threshold variations on transistor mismatch through Monte Carlo simulations. Various parameters like write margin and write 1 delay are validated against 30 mV sigma variation in threshold voltage for 2k data points at three different temperatures. The latter undergoes further evaluation at different process corners. The comparative analysis includes various pre-existing SRAM cells, highlighting the superior performance of the WARD 9T cell.

Traditional von Neumann computing architectures suffer from high energy and lower speed as compared to the requirements of modern applications like those required in neural network accelerators. A modified differential eight transistor (8 + T) static random access memory (SRAM)-based in-memory computing (IMC) structure was presented for realizing bit-wise Boolean logic operations. The 8 + T SRAM-IMC is designed at the 32 nm technology node with throughput of 2.1849, 2.4815, 2.5795, 2.6240, 2.6495, 2.6619, 2.6690, 2.6732, and 2.6749 giga outputs per second for 0.5 to 1.3 V supply voltage range, respectively. The differential 8T cell used to implement logic operations supports NAND and NOR operations with minimal overhead while also performing the standard storage operation with added stability over the conventional 6T and 8T SRAM cells. The SRAM-IMC offers reliable Boolean logic operations by using asymmetric sensing strategy for all process corners, TT, SS, SF, FS, and FF for an operating temperature range of 220 K to 400 K. Monte Carlo simulation considering global threshold voltage deviation of 50 mV was performed for various operating conditions to study the impact of variations on design parameters such as latency.

A modified decoupled sense amplifier (MDSA) and modified decoupled sense amplifier with NMOS foot-switch is proposed for improved sensing in differential SRAM for low-voltage operation at the 22-nm technology node. The MDSA and MDSANF both offer notable improvements to read delay over conventional voltage and current sense amplifiers. At an operating voltage of 0.8 V, the MDSA exhibited a reduced delay of 28.6%, 41.79%, 37.74%, and 30.94% compared to modified clamped sense amplifier (MCSA), double tail sense amplifier (DTSA), modified hybrid sense amplifier (MHSA), and conventional latch-type sense amplifier (LSA), respectively. Similarly, the MDSANF demonstrated a delay reduction of 26.13%, 39.78%, 35.58%, and 28.55% over MCSA, DTSA, MHSA, and LSA, respectively. To validate the performance, the MDSA and MDSANF are evaluated using the variation in delay and power consumption across various supply voltages, process corners, input differential bit line voltage (ΔV BL ), bit line capacitance (C BL ), and the sizing of decoupling transistors. Monte Carlo simulations were conducted to analyse the impact of voltage threshold variations on transistor mismatch which leads to an increased occurrence of read failures and a decline in SRAM yield. The performance analysis of various voltage and current sense amplifiers is presented along with MDSA and MDSANF. Area consideration for selection of sensing scheme is important and as such layout of MDSA and MDSANF was performed conforming to the design rules and estimated area for MDSA is 0.297 μm 2 whereas MDSANF occupies 0.5192 μm 2 .