The pursuit of miniature energy-efficient chips, and push for scaled voltages leads to increased timing errors that threaten the correct system functionality. Conventional error mitigation schemes based on redundancy, require costly and disruptive design changes, while they detect errors after they occur requiring expensive follow up correction schemes. In contrast to existing approaches, this paper introduces ePredictNet, an accurate workload-aware error-predictor based on compressed neural networks that can estimate early error prone instructions and avoid the manifestation of errors even under scaled voltages. Our work shows for the first time that accurate error prediction models are realizable on hardware with very low cost. This is achieved by training a quantized neural network that is converted to a netlist of truth tables using LogicNets, which can efficiently be mapped on circuit. Our results indicate, that ePredictNet once mapped on FPGA can achieve 99.39% error classification accuracy while utilizing only 270 LUTs and comes with only 2.1% area and 5% power overhead once integrated with a RISC core and costs up-to 98% less than the area and power incurred by redundancy based schemes. Apart from a cost effective error estimation scheme, ePredictNet can be used to avoid errors by guiding complimentary error mitigation schemes. For instance, in a power conscious use case,ePredictNet can allow the operation of a Open-RISC core under 12% reduced voltage, allowing to save 17% power with minimal 2.7% throughput reduction and guide the dynamic relaxation of frequency for avoiding errors only once error-prone instructions are predicted.

Recent advancements in hardware and software systems have been driven by the deployment of emerging smart health and mobility applications. These developments have modernized the traditional approaches by replacing conventional computing systems with cyber-physical and intelligent systems combining the Internet of Things (IoT) with Edge Artificial Intelligence. Despite the many advantages and opportunities of these systems within various application domains, the scarcity of energy, extensive computing needs, and limited communication must be considered when orchestrating their deployment. Inducing savings in these directions is central to the Approximate Computing (AxC) paradigm, in which the accuracy of some operations is traded off with energy, latency, and/or communication reductions. Unfortunately, the dynamics of the environments in which AxC-equipped IoT systems operate have been paid little attention. We bridge this gap by surveying adaptive AxC techniques applied to three emerging application domains, namely autonomous driving, smart sensing and wearables, and positioning, paying special attention to hardware acceleration. We discuss the challenges of such applications, how adaptive AxC can aid their deployment, and which savings it can bring based on traits of the data and devices involved. Insights arising thereof may serve as inspiration to researchers, engineers, and students active within the considered domains.

The design of low-power digital signal processing (DSP) architectures have gained a lot of attention due to their use in a variety of smart edge applications and portable devices. Recent efforts have focused on the replacement of power-hungry multipliers with various approximation frameworks such as multiplierless architectures that require only a few bit-shifts, additions and/or multiplexers when the multiplicand coefficients are known a priori. However, most existing multiplierless and approximation-based works have not been combined systematically with voltage over-scaling (VOS), which is considered one of the most effective power saving approaches, while the few that have tried, were applied to specific case studies with custom modifications. In this article, we are proposing a generic optimization framework that not only minimizes the hardware units in any time-multiplexed directed acyclic graph (TM-DAG) multiplier but also allows the reliable completion of most operations and the avoidance of random timing errors under VOS. This is achieved by synthesizing alternative coefficients that approximate well the original ones, while also activating shorter critical paths. As a result when VOS is applied, minor quality degradation occurs due to the coefficient approximations which are deterministic by design, while the gained timing slack of the new multiplicands allow us to reduce the supply voltage and circumvent the random timing errors induced by the increased delay under iso-frequency/throughput. Our experiments have indicated that when our framework is applied on fast Fourier transform (FFT) and discrete cosine transform (DCT) architectures, it results in up to 34.07% power savings, when compared to conventional multiplierless architectures, while it induces minimal signal-to-noise ratio (SNR) degradation, even when voltage is reduced by up to 20%.

Voltage over-scaling (VoS) may be one of the most effective power reduction approaches, however, it makes circuits susceptible to timing failures. Various techniques were proposed to facilitate VoS by detecting and correcting errors and moving away from traditional voltage and timing guardbands. However, such approaches require the addition of extra redundant hardware leading to area and power overheads, especially in case of large timing errors. Recent, complementary approaches tried to redesign the target circuits, however, they were not yet applied on complex pipelined architectures like floating point multiplier which is extensively used in neural networks and other popular applications. In this paper, we develop a low-power pipelined floating-point IEEE-754 compatible multiplier that can operate reliably under voltage over-scaling (VoS). This is achieved by applying a path-shaping approach that helps minimize the number of paths susceptible to timing errors under lower voltages. In addition, our micro-architectural modifications isolate the critical paths only to a single pipeline stage, thus minimizing the error-prone stages under VoS. To showcase the efficacy of our approach, we perform post-place dynamic timing analysis using various benchmarks, indicating that our design can lead up to 171% better SNR, 80% less BER and 36% less power under 18% less voltage compared to the baseline multiplier. The applied analysis reveals that our approach can help limit the erroneous outputs of the unit by up to 74% and reduce by 20% the multi-bit error probability, in such a widely used arithmetic unit.