Optimizing power, performance, and area in IC designs remains a key focus. However, the limited functionality of standard cell libraries restricts further optimization. A promising solution involves developing customized complex gates that integrate multiple basic gate functions into a single gate at the transistor level. While prior research has extensively explored transistor network optimization of the complex gates, most studies still focus on 1-stage networks, limiting the potential for deeper optimization. Furthermore, existing methodologies often neglect considering transistor placement during network synthesis, potentially leading to suboptimal area even if the transistor count is reduced. To address these limitations, we propose MuSTNet, a SAT-based exact synthesis framework that minimizing transistor networks by incorporating two key innovations: (1) multi-stage hierarchy for deeper optimization, and (2) transistor placement constraints to simultaneously minimize both transistor count and physical area. Experimental results demonstrate that MuSTNet surpasses previous studies, achieving an 18% reduction in transistor count for 4-input P-class functions and a 12.9% reduction for multi-output functions. When applied to an industrial library benchmark, MuSTNet yields a 6.3% area reduction compared to the approach neglecting placement constraints. Moreover, MuSTNet has been applied to complex gate generation, allowing simultaneous functional and topological optimization at the transistor level. Compared to traditional cell-level design, this approach reduces transistor count by 12.3% and area by 21.4%, demonstrating its potential in advanced IC design.

With the advance of technology nodes, via fabrication in a dense design becomes a difficult challenge, and the directed self-assembly (DSA) technology has shown its great potential in contact/via layer manufacturing. As many studies consider the guiding template design problem for cylindrical DSA, lamellar DSA with the self-aligned via process emerges as an alternative with better yield and design flexibility. However, the new process also imposes new constraints on template design, making an arbitrary contact/via layout suffer from unsatisfactory manufacturability. In this paper, we present the first work on detailed routing considering lamellar DSA guiding template design and mask assignment with double patterning lithography (DPL) to minimize the numbers of unmanufacturable vias and short templates. In the proposed router, we construct a conflict graph and a via forbidden map for routing guidance and via mask assignment. A prerouting methodology is developed to obtain better via distribution in critical areas and preserve routing space for further detailed routing. After that, a short template-aware detailed routing approach routes the rest of the nets and an existing template design engine is adopted for optimal template design and mask assignment. The experimental results indicate that compared to a conventional A*search-based router, our approach can generate conflict-free template design results and achieve 35% reduction in short templates.