Test coverage degradation from uncontrollable I/Os is a critical challenge in modern SoC design. In area-sensitive applications, such as the peripheral circuits of memory devices, standard DFT solutions like wrapper chains are prohibitively expensive due to their high area overhead. This necessitates a surgical Test Point Insertion (TPI) strategy that maximizes testability while adhering to strict cost constraints. To address this challenge, we propose a novel TPI framework using an explainable Graph Neural Network (GNN). Our GNN accurately predicts test coverage in circuits with masked I/Os, and an integrated saliency map (XAI) technique then identifies the most critical I/Os for TPI. Compared to a leading commercial tool, our framework achieves the target test coverage with 7.53% fewer TPs and improves coverage by 4.34% with the same TP budget on average. The scalability on large circuits (>100k gates) and technology independence confirm its practical applicability for minimizing die cost in constrained, real-world designs.

With the increasing demand for on-device Artificial Intelligence (AI), various compression schemes have been proposed for DNN models to be efficiently executed on mobile devices. Although various studies have proposed compression schemes, their compatibility with mobile device memory (i.e., LPDDR) is not considered; LPDDR is prone to error as it operates at low voltage due to its strict power constraint. Currently, DRAM vendors adopt an ECC engine with SEC(136,128) code inside each LPDDR bank (i.e., IECC) for reliable operation. While IECC enhances reliability, it lowers performance due to Read-Modify-Write (RMW) and parity storage costs. Thus, for both power-efficient and reliable DNN operation in mobile environments, this paper introduces LOCo, a DNN weight compression scheme with 3-staged protection. LOCo reduces the IECC engine operation granularity from SEC(136,128) to SECDED(72,64), thus eliminating power-intensive internal reads but enhancing reliability. To mitigate the storage overhead, this paper proposes a compression scheme with protection based on the characteristics of DNN weights. Our evaluations show that LOCo provides a power reduction of 16.94%, latency reduction of 16.81%, and energy reduction of 30.81% when compared to conventional LPDDR with SEC engine, while demonstrating robustness under 17959X more bit error rate when compared to existing compression scheme.

Deep Neural Networks (DNNs) are deployed in many real-time and safety-critical applications such as autonomous vehicles and medical diagnosis. In such applications, quantization is used to compress the model for storage and computation reduction. However, recent research has shown that faults in memory can cause a significant drop in DNN accuracy and conventional quantization methods focus only on model compression. This paper proposes a novel method that performs model quantization while remarkably improving the fault-tolerance of the model. It can be incorporated with other hardware approaches such as Error Correcting Code to further improve fault-tolerance. The proposed method reduces possible error patterns that negatively impact classification accuracy by modifying weight distributions and applying a novel masking-based clipping function. Experimental results show that the proposed method enhances the fault-tolerance of the quantized DNN, which can tolerate 1803× higher bit error rates than the conventional method.

This paper proposes a novel memory architecture, PIE-DRAM, to mitigate the performance overhead caused by IECC. Unlike conventional IECC architectures, the proposed method separates IECC from data path to enable independent IECC operations from memory read or write access. Based on recent memory access histories, memory controller selectively determines the usage of IECC to alleviate IECC overhead, thereby the proposed architecture enhances the memory performance. Experimental results show that, from memory intensive workloads, 6% IPC (Instructions Per Cycle) improvement is achieved solely by applying the proposed DRAM architecture utilizing the locality and modified RMW.