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Xiaotian Tian

dblp:357/2675 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2023
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 61% High-performance computing · 30% Emerging computing paradigms · 9%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
High-performance computing › iterative methods
algebraic multigrid
0.712023
AmgR: Algebraic Multigrid Accelerated on ReRAM · DAC 2023
Memory systems
processing-in-memory
0.712023
AmgR: Algebraic Multigrid Accelerated on ReRAM · DAC 2023
Memory systems › processing-in-memory
ReRAM-based processing-in-memory
0.712023
AmgR: Algebraic Multigrid Accelerated on ReRAM · DAC 2023
Emerging computing paradigms
non-von neumann architecture
0.212023
AmgR: Algebraic Multigrid Accelerated on ReRAM · DAC 2023

Methods — techniques the papers use, named apart from their topics

write reduction · 0.7aggregation unit design · 0.7ReRAM mapping · 0.7
YearPublicationVenuePosition
2023 AmgR: Algebraic Multigrid Accelerated on ReRAM
abstract
Solving systems of linear equations is a fundamental problem in scientific computing, which has been extensively researched for decades. One of the most well-known solvers is Algebraic Multigrid (AMG), which is widely used in high performance computing due to its good scalability. But currently accelerating AMG relies on the traditional von Neumann architecture of storage and computation separation, which leads to a large data transmission overhead. In this work, we propose a ReRAM-based processing-in-memory (PIM) architecture named AmgR, which overcomes the limitations of the traditional von Neumann architecture for AMG acceleration.However, accelerating AMG on ReRAM is non-trivial, because (1) AMG has many computing kernels of various types; (2) there are irregular operations that cannot be directly performed using matrix-vector multiplication suitable for ReRAM, i.e., aggregation operation; (3) ReRAM has poor write endurance, and a lot of data during AMG acceleration needs to be rewritten into ReRAM, resulting in high write cost. To address these issues, firstly, we propose a flexible architecture, which can realize each kernel of AMG and is reused by many kernels to improve resource utilization. Secondly, we propose a dedicated unit to realize the aggregation operation. Finally, we present a new mapping strategy to greatly reduce the number of data handling and writes. The experimental results show that the performance of AmgR is improved by an average of one and two orders of magnitude compared to HYPRE on the CPU and AmgX on the GPU, respectively, while the energy consumption is reduced by an average of two and three orders of magnitude.
Mingjia Fan, Xiaotian Tian, Yintao He, Yiru Duan, Xiaozhe Hu, Ying Wang 0001, Zhou Jin 0001, Weifeng Liu 0002
DAC2