MBFF banking is a standard technique for clock power reduction in modern IC design, yet two systemic flaws in prior works limit its practical gains: geometric abstractions that ignore placement congestion, and open-loop workflows where late legalization failures nullify power savings. We propose a self-correcting framework that co-optimizes banking, placement, and debanking via three innovations: (1) Mahalanobis-distance clustering for placement-feasible MBFF formation; (2) a legalization-driven feedback loop with cost-aware debanking to recover unplaceable MBFFs; and (3) an OPTICS-based debanking that splits problematic MBFFs at highest-cost boundaries. Evaluated on ICCAD 2024 CAD Contest Problem B and large-scale benchmarks, our framework outperforms the 1st, 2nd, and 3rd place winners by 2.3%, 9.3%, and 4.0% in final weighted score, respectively.

Legalization holds significant importance in VLSI physical design, as it significantly influences the manufacturability and reliability of circuits. Recently, advanced foundry nodes introduced complex constraints in standard-cell legalization, which makes legalization even harder. In this paper, we develop a legalization framework with design rule constraints enhanced by Monte-Carlo-Based cell priority optimization. We first handle abnormal density distribution to reduce the subsequent legalization’s hardness. Then, we propose an interval-assisted sequential legalization algorithm considering multiple design rule constraints with a Monte-Carlo-Based cell priority decision technique. Besides, based on the characteristics and complexity of different design rule constraints, we present a refinement phase to handle the remaining design rule constraints with corresponding detectors. Compared with a leading commercial tool, experiments on industrial benchmarks show that our legalization framework achieves 11% smaller average displacement, 15% smaller maximum displacement, 1.63× speedup, and 13% fewer remaining design rule violations on average.

Recently, hybrid-row-height designs have been introduced to achieve performance and area co-optimization in advanced nodes. Hybrid-row-height designs incur challenging issues to layout due to the heterogeneous cell and row structures. In this paper, we present an effective algorithm to address the hybrid-row-height placement problem in two major stages: (1) global placement, and (2) legalization. Inspired by the multi-channel processing method in convolutional neural networks (CNN), we use the feature extraction technique to equivalently transform the hybrid-row-height global placement problem into two sub-problems that can be solved effectively. We propose a multi-layer nonlinear framework with alignment guidance and a self-adaptive parameter adjustment scheme, which can obtain a high-quality solution to the hybrid-row-height global placement problem. In the legalization stage, we formulate the hybrid-row-height legalization problem into a convex quadratic programming (QP) problem, then apply the robust modulus-based matrix splitting iteration method (RMMSIM) to solve the QP efficiently. After RMMSIM-based global legalization, Tetris-like allocation is used to resolve remaining physical violations. Compared with the state-of-the-art work, experiments on the 2015 ISPD Contest benchmarks show that our algorithm can achieve 7%; shorter final total wirelength and $2.23 \times $ speedup.

As technology scales down, multi-cell spacing constraints are imposed by modern circuit designs. Previous works compromise solution quality to address the problem by transforming it into two-cell spacing constraints. In this paper, we propose a detailed placement algorithm considering multi-cell spacing constraints. First, an SAT-based multi-cell spacing violation reduction method is presented to reduce the number of violations with minimum displacement. Then, a window-based violation elimination method is adopted to resolve all the remaining violations. Finally, we refine the placement result with ILP to reduce the cell displacement. Compared with the state-of-the-art work, experimental results show that our algorithm achieves a 19% improvement in displacement and a 39% reduction in runtime.

In modern circuits, mixed-cell-height standard cells have been prevailing to meet various requirements and achieve better trade-offs among timing, power, and routability. Besides, the constraints of the minimum-implant-area (MIA) and drain-to-drain-abutment (DDA) arise as emerging challenges at advanced technology nodes. In this paper, we present an algorithm to address the mixed-cell-height placement problem with MIA and DDA constraints in three major stages: (1) post-global placement, (2) legalization, and (3) detailed placement. In the post-global stage, we first align mixed-cell-height standard cells to the desired rows by conjugate gradient method with dynamic step size and then reorder them by the shortest path algorithm to distribute the source nodes evenly. In the legalization stage, we propose a two-step combination algorithm to cluster cells and repack the clusters to minimize the wirelength, after which we presented a queue based method to address the inter-row MIA violations. In the detailed placement, an MIA-aware DDA reduction algorithm is adopted after multi-region partitioning to eliminate DDA violations without introducing MIA violations. Experimental results show that our algorithm can resolve all MIA and almost all DDA violations with a 13% reduction in displacement, a 4% reduction in HPWL, and 25% less runtime compared with the state-of-the-art work.