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Yiyang Wu

dblp:357/2762 · DBLP profile ↗
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4ranked-venue papers
1as first author
4since 2021 · last 2026
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 3 since 2021Artificial intelligence and machine learning · 1 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Databases, data mining, and information retrieval
1 paper
Graph data management · 67% Data stream processing · 33%
Network and information security
1 paper
Systems and software security · 100%
Software engineering, system software, and programming languages
1 paper
Operating systems · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 77% Reconfigurable computing and FPGAs · 23%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Systems and software security
firmware security
0.912025
μEFI: A Microkernel-Style UEFI with Isolation and Transparency · USENIX ATC 2025
Operating systems › kernel › kernel design
microkernel
0.912025
μEFI: A Microkernel-Style UEFI with Isolation and Transparency · USENIX ATC 2025
Graph data management
graph processing
0.812024
LSGraph: A Locality-centric High-performance Streaming Graph Engine · EuroSys 2024
Data stream processing
streaming graph
0.812024
LSGraph: A Locality-centric High-performance Streaming Graph Engine · EuroSys 2024
Graph data management › graph analytics
streaming graph analysis
0.812024
LSGraph: A Locality-centric High-performance Streaming Graph Engine · EuroSys 2024
Hardware accelerators and domain-specific architectures
graph processing accelerator
0.712023
SaGraph: A Similarity-aware Hardware Accelerator for Temporal Graph Processing · DAC 2023
Reconfigurable computing and FPGAs
FPGA accelerator
0.212023
SaGraph: A Similarity-aware Hardware Accelerator for Temporal Graph Processing · DAC 2023

Methods — techniques the papers use, named apart from their topics

locality-centric data layout · 0.8similarity-aware caching · 0.7dynamic coordination · 0.7
YearPublicationVenuePosition
2026 An integration framework for gait-emotion recognition: Combining cognitive insights with neural networks
Yiyang Wu, Xuechen Yu, Shu-Guang Kuai
Eng. Appl. Artif. Intell.1
2025 μEFI: A Microkernel-Style UEFI with Isolation and Transparency
Yiyang Wu, Jinyu Gu 0001, Yubin Xia, Haibo Chen 0001
USENIX ATC2
2024 LSGraph: A Locality-centric High-performance Streaming Graph Engine
abstract
Streaming graph has been broadly employed across various application domains. It involves updating edges to the graph and then performing analytics on the updated graph. However, existing solutions either suffer from poor data locality and high computation complexity for streaming graph analytics, or need high overhead to search and move graph data to ensure ordered neighbors during streaming graph update.
Hao Qi 0004, Yiyang Wu, Ligang He, Yu Zhang 0027, Minzhi Cai, Hai Jin 0001, Zhan Zhang 0003, Jin Zhao 0003
EuroSys2
2023 SaGraph: A Similarity-aware Hardware Accelerator for Temporal Graph Processing
abstract
Temporal graph processing is used to handle the snapshots of the temporal graph, which concerns changes in graph over time. Although several software/hardware solutions have been designed for efficient temporal graph processing, they still suffer from serious irregular data access due to the uncoordinated graph traversal. To overcome these limitations, this paper proposes SaGraph, a domain-specific hardware accelerator to support the efficient processing of temporal graph. Specifically, temporal graph processing shows strong data access similarity, i.e., most graph accesses of the processing of different snapshots are the same and usually refer to a small fraction of vertices. SaGraph can dynamically coordinate the graph traversals and adaptively cache the vertex states to fully exploit the data access similarity for smaller data access overhead. We implemented and evaluated SaGraph on a Xilinx Alveo U280 FPGA card. Compared with the cutting-edge software and hardware solutions, SaGraph achieves 8.5×-157.3×, 4.2×-16.1× speedups and 34.7×-423.6×, 5.3×-14.7× energy savings, respectively.
Jin Zhao 0003, Yu Zhang 0027, Yiyang Wu, Chuyue Ye, Zhiying Huang, Hai Jin 0001, Xiaofei Liao, Lin Gu 0002, Haikun Liu
DAC4