Coarse-Grained Reconfigurable Arrays (CGRAs) play an important role in accelerating computation-intensive applications due to their flexibility and power efficiency. Most existing mapping works for CGRA assume that all the data of a loop kernel can be previously moved from DRAM to ScratchPad Memory (SPM) with one data transfer. However, when targeting low-power CGRAs, the SPM can hardly hold the entire data even for a small loop kernel, and it inevitably incurs multiple data transfers, leading to notable costs. In this case, where and how to perform data transfer considering the DRAM access behavior is crucial to the overall execution performance. To this end, this paper proposes a data transfer optimization method to simultaneously optimize loop pipelining and data transfer. Since there is an interplay between loop structure and data transfer, we establish an optimization problem considering both polyhedral transformation and transfer strategy exploration, offering opportunities to find the near-optimal data transfer strategy within the search space. The experimental results show that compared with existing methods, our method can achieve 1.36×–4.55× speedup for loop kernels with different on-chip buffer sizes, and only increase the compilation time by a small amount.

Coarse-grained reconfigurable arrays (CGRAs) can provide high energy efficiency while maintaining flexibility, which is promising to keep pace with the power requirements and the frequent updates of applicants. With flexible register chains, modern CGRAs enable data reuse within the processing element array (PEA) to reduce on-chip memory accesses and improve pipelining performance. However, existing works pay little attention to comprehensive loop transformations, such as affine and nonaffine transformation, to obtain a data reuse-friendly loop structure. Therefore, this article proposes a data-reuse-friendly loop mapping approach using joint affine and nonaffine transformations. With affine transformations, the distance of loop dependencies could be reduced and then handled by in-PEA routes. With nonaffine transformations (i.e., loop unrolling), small loop kernels could be unrolled and expose more memory accesses for data reuse. To efficiently solve the loop transformation problem, we first establish a reduced polyhedral formulation and then propose a divide-and-conquer-based solution to find optimized transformations with moderate compilation time. Experimental results demonstrate that our approach can achieve a speedup up to$1.74\times $compared to state-of-the-art methods.

Coarse-Grained Reconfigurable Arrays (CGRA) can provide high energy efficiency while keeping moderate flexibility. With flexible connections, modern CGRAs are allowed to construct register chains on demand such that data reuse could be achieved. However, existing works put little effort into loop transformations for better data reuse. Therefore, this paper proposes an efficient loop transformation approach considering data reuse for the overall performance. Using reduced polyhedral formulation and Dynamical Programming (DP) based searching, loop structures could be thoroughly and efficiently explored for optimized solutions. The experimental results show that our approach can achieve 1.11-1.15 × speedup compared to the state-of-the-art approach.