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EDBT 2026 Demo / reviewers in the wild / expert

Marcus Pan

dblp:357/2876 · DBLP profile ↗
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1ranked-venue papers
1as first author
1since 2021 · last 2023
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 38% Integrated circuit design · 38% Energy-efficient computing · 23%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
heterogeneous integration		 0.712023
System-level Innovation for the Next Decade AI Performance, Power, Area with Co-optimization · DAC 2023
Energy-efficient computing
power management		 0.212023
System-level Innovation for the Next Decade AI Performance, Power, Area with Co-optimization · DAC 2023
Energy-efficient computing › power management › system-level power management
system-level power optimization		 0.212023
System-level Innovation for the Next Decade AI Performance, Power, Area with Co-optimization · DAC 2023

Methods — techniques the papers use, named apart from their topics

machine learning · 0.7
YearPublicationVenuePosition
2023 System-level Innovation for the Next Decade AI Performance, Power, Area with Co-optimization
abstract
Power, performance, and area (PPA) are three key parameters in conventional system-on-chip design optimization. In post Moore’s law era, system-level PPA improvement for system-of-chips/chiplets – a new "SoC" – relies on multi-disciplinary AI co-optimization across full stack innovations including process-in memory, edge intelligent sensing and heterogenous integration.
Marcus Pan
 DAC1