Physical design tools have complex workflows with many different ways of optimizing power, performance, and area (PPA) out of a large number of options and hyperparameters in different engines and functionalities. Black-box optimization techniques are widely adopted to automate quality-of-result (QoR) exploration. Such exploration often proves impractical in real-world customer environments due to high computational demands, lengthy exploration cycles, and the need for large parallel jobs. To reduce the exploration space for viable compute resource requirements, we propose a novel design methodology to enable transferable learning by incorporating design insights crafted on top of physical design experts’ experience and streamlining QoR exploration as a sequence generation task for best recipe selection. We apply language model-inspired alignment techniques to learn the ranking of different recipe sets, enabling our model to generalize beyond known-good manually tuned expert design recipes. Extensive evaluations demonstrate our method’s superior QoRs and runtime performance on unseen industrial designs and rigorous benchmarks.

Few engineering challenges are as complex and arduous as chip design, which typically requires multiple teams of experts and months of dedicated and diligent PPA (Performance, Power and Area) exploration work to achieve the desired goal. In the era of pervasive AI, Chip design automation tools are witnessing a seismic shift, emerging as a powerful intelligent AI agent that orchestrates various decision-making process at every aspect of chip design flow by leveraging multiple computes to explore different PPA strategies. This radical shift demands an AI ecosystem that connects data storage, compute resources, real time data analytics and efficient search space navigation technologies. In this talk, we will explore how physical design implementation tools are embracing AI agents to drive PPA exploration by using novel reinforcement learning techniques powered by deep insights of design and flow execution experience of prior run. The core of such system is built on continuous learning paradigm so that with each successive iteration of the same design, the system learns and adapts and delivers consistent PPA improvement.

Concurrent Clock and Data (CCD) optimization is a well-adopted approach in modern commercial tools that resolves timing violations using a mixture of clock skewing and delay fixing strategies. However, existing CCD algorithms are flawed. Particularly, they fail to prioritize violating endpoints for different optimization strategies correctly, leading to flow-wise globally sub-optimal results. In this paper, we overcome this issue by presenting RL-CCD, a Reinforcement Learning (RL) agent that selects endpoints for useful skew prioritization using the proposed EP-GNN, an endpoint-oriented Graph Neural Network (GNN) model, and a Transformer-based self-supervised attention mechanism. Experimental results on 19 industrial designs in 5 − 12nm technologies demonstrate that RL-CCD achieves up to 64% Total Negative Slack (TNS) reduction and 66.5% number of violating endpoints (NVE) improvement over the native implementation of a commercial tool.