Chiplets promise customized design for different sets of applications with heterogeneity, where there are various kinds of resources to manage. Examples are GPUs, NPUs, and CPUs for computation of AI and general tasks, memory, communication, as well as logical resources such as I/Os. There can be strong contention in access of resources across chiplets by applications, which sometimes have discrepant requirements. Resolving such contention is critical to fully exploit the resources on heterogeneous chiplets and satisfy the needs of dynamic application workloads. This talk will discuss a set of methods that manage these resources during the design phase as well as at runtime, which should interact with the architecture exploration and contribute to the entire chiplets systems design altogether.

WCET (Worst-Case Execution Time) estimation on multicore architecture is particularly challenging mainly due to the complex accesses over cache shared by multiple cores. Existing analysis identifies possible contentions between parallel tasks by leveraging the partial order of the tasks or their program regions. Unfortunately, they overestimate the number of cache misses caused by a remote block access without considering the actual cache state and the number of accesses. This paper reports a new analysis for inter-core cache contention. Based on the order of program regions in a task, we first identify memory references that could be affected if a remote access occurs in a region. Afterwards, a fine-grained contention analysis is constructed that computes the number of cache misses based on the access quantity of local and remote blocks. We demonstrate that the overall inter-core cache interference of a task can be obtained via dynamic programming. Experiments show that compared to existing methods, the proposed analysis reduces inter-core cache interference and WCET estimations by$\mathbf{5 2. 3 1 \%}$and$\mathbf{8. 9 4 \%}$on average, without significantly increasing computation overhead.

Directed Acyclic Graph (DAG) models are extensively utilized across fields such as automotive, wireless communication, and deep learning, to capture the inherent functional dependencies. Topology of DAG has a significant impact on the performance of scheduling and resource management algorithms applied to it. Hence, it is imperative to generate all DAG topologies within the parameter ranges pertinent to an application domain, for impartial evaluation of such algorithms. Unfortunately, the existing DAG generators that are capable of offering full topology coverage have limited scalability and controllable parameters. This work reports open-source FT-DAG, an efficient and formally verified full-topology DAG generator that is able to control all major parameters, including the longest length, shortest length, width, jump layer, jump level, in-degree, out-degree, shape value as well as the number of nodes and edges. Experiments show that when the number of nodes is larger than 20, FT-DAG provides at least two orders of magnitude speedup compared to the state of the art and more orders to other generators. FT-DAG scales to 100 nodes in a typical industrial case study within hours.

Many complex real-time systems, such as increasingly automated vehicles and 5G wireless base stations, contain a large amount of shared resources that must be accessed in a mutually exclusive fashion. This leads to significant contention especially when resources are shared across processors. To reduce the contention, various resource-aware task allocation methods have been developed to localize the shared resources. Unfortunately, these existing methods either are tailored for specific scheduling and analysis approaches, or introduce runtime overhead that undermines their applicability. In this paper, we present a task allocation method for a mainstream type of real-time systems in practice: FP-FPS (fully-partitioned fixed-priority scheduling) multiprocessor systems with spin locks managing shared resources. Instead of relying on timing bounds as guidance, we utilize a model to approximate the degree of resource contention between tasks. The model is decoupled from priority assignment algorithms, resource sharing protocols and schedulability tests. Hence, our task allocation method can be applied without detailed knowledge of the underlying system, which is particularly useful during the initial design phase of the system. More detailed information about the system in the later phases of design will push up the approximation accuracy and further enhance the performance. Experimental results show that the proposed method outperforms the state-of-the-art by 13.6% on average (up to 24.2%) in system schedulability with a much less (57x on average) computation cost and negligible runtime overhead.

The increasing computational demand promotes the application of parallel tasks with complex execution dependencies in industrial applications. The Directed Acyclic Graph (DAG) task model is widely applied with dedicated scheduling algorithms to understand and manage the execution of such systems. In order to validate the effectiveness of different DAG scheduling algorithms, DAG generators are often applied to produce synthesized DAGs for performance evaluation. However, existing DAG generators either fail to provide sufficient topology coverage or suffer from severe scalability issues, leading to biased and incomplete evaluation results. This paper proposes a novel DAG generator that provides full topology coverage under the given DAG structural parameters while eliminating isomorphic DAGs as well as redundant edges in each DAG. In addition, a verification method is constructed that enables topology coverage, isomorphic DAG identification, and constraint satisfaction of the generated DAGs. The experimental results show that compared to existing generators, the proposed DAG generator achieves full topology coverage and significantly reduces the number of DAGs being produced. The DAG generator proposed in this work provides a complete solution for synthesised DAG generation, enabling fair and comprehensive evaluation of DAG systems.