In this work, we present single-event upset (SEU) analysis for Forksheet FET (FSFET) based CMOS circuits. Next, we present an array-level power and performance analysis along with the Vminevaluation for the FSFET-based SRAM. Physics based TCAD and industry-standard BSIM-CMG compact models are calibrated for accurate circuit analysis in SPICE. The impact of varying Heavy-Ion Radiation (HIR) doses and strike orientations is investigated for the FSFETs. The robustness of CMOS inverter against HIR is also reported in terms of failure time (tfail) and output voltage swing ($Δ$VDrop). For the SRAM, we determine the critical Linear Energy Transfer (LET). For FSFET, the individual n-/p-FETs are more vulnerable to the irradiation incident on nearby devices. At the circuit level, in comparison to perpendicular strikes, the$Δ$VDropincreases by 1.25V and 2.75V respectively, for oblique and transverse incidences, at a dose of 2.0MeVcm2/mg. The tfail also increases by 43% and 60% and the SRAM critical LET also decreases by 85% and 57.5%, respectively. The array level SRAM evaluation shows that the FSFET enables reliable operation with low-power consumption, impressive noise margins, and low minimum operating voltage (Vmin) values. FSFET SRAM power dissipation during the read and write operations is as low as 7.02$μ$W, and 3.00$μ$W respectively. At VDD=0.70V, the noise margins for hold, read, and write operations are 289.27mV, 122.89mV, and 297.79mV. The Vminfor read and write operations are 0.30V and 0.35V respectively.

In this paper, we have proposed a negative capacitance (NC) L shaped channel tunnel field-effect transistor (NC-LTFET), which consists of a hafnium oxide$(\text{HfO}_{2})$based ferroelectric (FE) layer in the gate stack. The presence of polarization phenomena in the FE layer tends to enhance the internal voltage and electric field, which result higher ON-state current and steeper subthreshold swing (SS). From well calibrated 2-D TCAD simulation results, it is revealed that the NC-LTFET outperforms the conventional LTFET in terms of both static and dynamic energy dissipation. The NC-LTFET exhibits$\sim 430 \times$and$\sim 10^{4} \times$higher ON-state current and$I_{O N} / I_{O F F}$ratio, respectively, as compared to the conventional LTFET. In addition, the proposed NC-LTFET shows$\sim 2.2 \times, \sim 10^{2} \times$and$\{\sim} 10^{2} \times$low SS, switching delay and energy delay product (EDP), respectively as compared to the conventional LTFET. As a result, NC-LTFET is$10 \times$higher energy efficient for both memory and logic designs switching at ultra-low supply voltage$(<0.2 ~\mathrm{V})$when compared to the conventional MOSFET and LTFET.