Demo Data from EDBT 2026 / reviewers in the wild / expert
Emilien Bauer
dblp:358/6571
· DBLP profile ↗
2ranked-venue papers
0as first author
2since 2021 · last 2025
0009-0006-8028-3064ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Software engineering, systems software and programming languages · 2 · 2 since 2021Systems, architecture and hardware · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
2 papers |
Compilers and program optimization · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
High-performance computing · 56% Hardware accelerators and domain-specific architectures · 34% Parallel and multicore computing · 10% |
Topics — the 7 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Compilers and program optimization
code generation |
0.9 | 1 | 2025 | Compressed and Parallelized Structured Tensor Algebra · Proc. ACM Program. Lang. 2025 |
Compilers and program optimization › domain-specific compilation
tensor algebra compilation |
0.9 | 1 | 2025 | Compressed and Parallelized Structured Tensor Algebra · Proc. ACM Program. Lang. 2025 |
Hardware accelerators and domain-specific architectures
domain-specific compilers |
0.8 | 1 | 2024 | A shared compilation stack for distributed-memory parallelism in stencil DSLs · ASPLOS (3) 2024 |
High-performance computing
stencil computation |
0.8 | 1 | 2024 | A shared compilation stack for distributed-memory parallelism in stencil DSLs · ASPLOS (3) 2024 |
High-performance computing
scientific computing systems |
0.3 | 1 | 2025 | Compressed and Parallelized Structured Tensor Algebra · Proc. ACM Program. Lang. 2025 |
High-performance computing › tensor computation
tensor algebra |
0.3 | 1 | 2025 | Compressed and Parallelized Structured Tensor Algebra · Proc. ACM Program. Lang. 2025 |
Parallel and multicore computing › parallel programming models
message passing |
0.2 | 1 | 2024 | A shared compilation stack for distributed-memory parallelism in stencil DSLs · ASPLOS (3) 2024 |
Methods — techniques the papers use, named apart from their topics
MLIR · 3.3polyhedral analysis · 1.7affine code generation · 1.7
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Compressed and Parallelized Structured Tensor AlgebraabstractTensor algebra is a crucial component for data-intensive workloads such as machine learning and scientific computing. As the complexity of data grows, scientists often encounter a dilemma between the highly specialized dense tensor algebra and efficient structure-aware algorithms provided by sparse tensor algebra. In this paper, we introduce DASTAC, a framework to propagate the tensors’s captured high-level structure down to low-level code generation by incorporating techniques such as automatic data layout compression, polyhedral analysis, and affine code generation. Our methodology reduces memory footprint by automatically detecting the best data layout, heavily benefits from polyhedral optimizations, leverages further optimizations, and enables parallelization through MLIR. Through extensive experimentation, we show that DASTAC can compete if not significantly outperform specialized hand-tuned implementation by experts. We observe 0.16x 44.83x and 1.37x - 243.78x speed-up for single- and multi-threaded cases, respectively. Mahdi Ghorbani, Emilien Bauer, Tobias Grosser, Amir Shaikhha |
Proc. ACM Program. Lang. | 2 |
| 2024 | A shared compilation stack for distributed-memory parallelism in stencil DSLsabstractDomain Specific Languages (DSLs) increase programmer productivity and provide high performance. Their targeted abstractions allow scientists to express problems at a high level, providing rich details that optimizing compilers can exploit to target current- and next-generation supercomputers. The convenience and performance of DSLs come with significant development and maintenance costs. The siloed design of DSL compilers and the resulting inability to benefit from shared infrastructure cause uncertainties around longevity and the adoption of DSLs at scale. By tailoring the broadly-adopted MLIR compiler framework to HPC, we bring the same synergies that the machine learning community already exploits across their DSLs (e.g. Tensorflow, PyTorch) to the finite-difference stencil HPC community. We introduce new HPC-specific abstractions for message passing targeting distributed stencil computations. We demonstrate the sharing of common components across three distinct HPC stencil-DSL compilers: Devito, PSyclone, and the Open Earth Compiler, showing that our framework generates high-performance executables based upon a shared compiler ecosystem. George Bisbas, Anton Lydike, Emilien Bauer, Nick Brown 0002, Mathieu Fehr, Lawrence Mitchell, Gabriel Rodriguez-Canal, Maurice Jamieson, Paul H. J. Kelly, Michel Steuwer, Tobias Grosser |
ASPLOS (3) | 3 |