This paper presents a current steering variable gain amplifier (VGA) in SiGe BiCMOS with a gain control circuit and a current mirror with negative feedback to avoid thermal runaway. The gain control circuit exploits a current steering topology, whereas a true exponential relationship between the currents of the emitter-and base-driven transistor is locked by a current mirror for gain compensation of the VGA until the highest gain setting. The VGA achieves a maximum measured gain of 21.5 dB and maximum gain control range (GCR) of 24.5 dB at 27 GHz, with an operation bandwidth from 15 GHz to 40 GHz. Within the bandwidth and full GCR, the measured phase error is 12.7°, and lower phase errors can be achieved for lower GCR, e.g., 4.4° for GCR of 14 dB, depending on the applications. The chip is very compact and occupies only 0.1 mm2. Thus, the proposed VGA can cover the entire millimetre-wave (mm-wave) 5G band and is suitable for integrating into phased-array systems due to its performance and compactness.

This paper presents an ultralow power-consumption, high data-rate continuous-phase frequency-shift-keying (CPFSK) transmitter (TX). The TX mainly consists of a high-speed digitally controlled oscillator (DCO), a pseudorandom bit sequence (PRBS) generator, a wideband input clock butter and a CML-to-CMOS converter. The DCO is used to generate two carrier frequencies of $\approx 70 {\mathrm{GHz}}$ and $\approx 75 {\mathrm{GHz}}$. In order to achieve a low power consumption, high quality (Q) - factor inductors and capacitors are deliberately implemented in the DCO, and a high-speed switch is designed to obtain a high data rate. A half-rate, fully-differential PRBS generator with asynchronous XOR is also integrated for testing purposes. The TX was implemented in TSMC 65 nm CMOS with a chip size of $0.8 {\mathrm{mm}} \times 0.6 {\mathrm{mm}}$. The highest data rate of 16 Gbps is measured in the frequency domain. The DC power consumption of 19.6 mW from a 1.2V supply voltage is measured without the PRBS generator leading to an energy efficiency per bit of 1.225 pJ/bit. Due to its low power consumption and high data rate, the proposed TX is suitable for indoor short-range wireless communication and could also be adapted for future 6G mobile communication.

This paper presents the research directions pursued by the WiPLASH European project, pioneering on-chip wireless communications as a disruptive enabler towards next-generation computing systems for artificial intelligence (AI). We illustrate the holistic approach driving our research efforts, which encompass expertises and abstraction levels ranging from physical design of embedded graphene antennas to system-level evaluation of wirelessly-communicating heterogeneous systems.

Isolation of switches is critical parameter for CMOS system-on-chip (SoC) transceivers. This paper presents a high-isolation stacked CMOS RF switch using dc-lift and feedforward cancellation techniques to improve isolation. The lifting resistors are employed to prevent the conduction of the junction diodes in the OFF state. Furthermore, by deliberately sizing these resistors multiple feedforward paths are created, which further improve isolation without using additional components. A single-pole single-throw (SPST) switch is implemented in a standard 65 nm CMOS process to demonstrate the concept. Measured isolation is 41 dB and insertion loss is less than 1.8 dB at 2.55 GHz. The active region is smaller than 0.02 mm2.

Large scale antenna systems (LSAS) in the mmWave bands provide a solution to the problems of spectrum shortage experienced in the conventional microwave bands. In a practical large scale antenna deployment, implementation of hybrid beamforming structures is very important as it provides high array gains to overcome the high path loss and achieve sufficient link margins. However, while implementing this we encounter the challenges such as complexity, cost and energy consumption. In this paper a power consumption model for the large scale antenna mmWave system is presented and analysed. From the power consumption model we maximize the energy efficiency of the overall system. Optimization of energy efficiency is a crucial factor in system optimization and design of the powerhungry devices. But with increasing energy efficiency, the spectral efficiency decreases. Thus analysis of the relation between energy and spectral efficiency becomes a critical task and we optimize energy efficiency at a fixed spectral efficiency. The results can then be utilized to guide the practical energy/spectrum efficiency trade-off for the LSAS design.

This paper presents a new approach to improve the accuracy of power amplifier or transmitter characterisation. Compared to traditional characterisation, an iterative characterisation approach using realistic excitation signals is introduced. Based upon this approach, more accurate nonlinear behaviour for AM/AM and AM/PM can be measured. A memoryless piecewise digital predistortion (DPD) model using iterative characterisation is built to linearise a power amplifier (PA). The linearity improvement by using the iterative characterisation approach is verified in measurements with LTE excitation signals on a PA at 2.05 GHz. For a 10 MHz 64-QAM LTE signal with a PAPR of 8.1 dB measured ACLR1 could be reduced with two additional steps from -41.6 dBc to -47.6 dBc. At the same time measured EVM was better than 4.2% for an average drain efficiency of 51%. Only few steps are required with the proposed linearisation approach to improve the linearity of components without extra complexity to the DPD.

This paper presents a digital centric transmitter architecture with clock domain transition from the baseband clock to a clock derived from the local oscillator of the proposed transmitter. Both clock domains are asynchronous and variable in general, hence this transistion block represents the key building block of the digital signal processing chain. It consists of a synchronizing stage, a timing control unit, and a modified Generalized Farrow upsample filter which allows to implement further upsample stages using simple integer-ratio CIC filters. The architecture is well appropriate for low energy digital-centric hardware designs. Highly reconfigurable, it is applied in a state-of-the-art multimode multistandard transmitter with radio frequency DAC frontend, suitable for WLAN, UMTS, LTE and other recent standards.