Fault-tolerant technology is becoming increasingly critical due to the growing complexity of computing systems and escalating demands for reliability. Conventional recovery mechanisms in asymmetric multiprocessor systems often incur substantial overhead or exhibit inefficiencies, such as prolonged rollback latency and complex synchronization protocols. This paper introduces an adaptive fast recovery scheme based on checkpoints that minimizes reliance on rollback by prioritizing roll-forward execution where feasible, while retaining rollback capabilities for severe failures. Using a triple modular redundancy system as a case study, we comprehensively detail the proposed scheme’s operation. By modeling fault occurrences via a Poisson process, we theoretically analyze the performance of conventional rollback algorithms against the proposed strategy. The scheme is implemented on an FPGA platform with heterogeneous processors (ARM, MIPS, and RISC-V), demonstrating practical synchronization across diverse architectures. Experimental results demonstrate that our scheme achieves over 10% reduction in average execution time compared to traditional rollback methods, thereby providing an efficient and hardware-validated fault-tolerant solution for advanced multiprocessor systems.

With the end of Moore’s law and Dennard scaling, waferscale systems or processors that integrate multiple pre-tested known good dies (KGDs) on a waferscale-interposer are new approaches to further improve the chiplet-based system’s performance. This article explores the network on wafer (NoW) architecture of waferscale switching system under several physical constraints. A software-based approach is proposed to redefine the topological property. A five-level butterfly fat-tree (BFT)-like logical topology with 8.96-Tb/s (896 ports$\times 10$Gb/s/port) switching bandwidth is achieved based on 2-D-mesh-like physical topology. We show that the proposed BFT-like topology with breadth-first-search (BFS) based traffic balanced routing algorithm reduces 55.6% hops, 41.4% transmission delay, and improves 24.2% throughput compared to 2-D-mesh-like topology under different traffic distributions. This BFT-like waferscale switching system is suitable for high-performance computing and data centers. In addition, the numerical analysis shows that the waferscale package can provide significant power efficiency and latency advantages compared to the typical single-chip package, which mainly benefits from the short-reach IO requirements. Note that the proposed waferscale switching system is compatible with high-switch-capacity dies with advanced process technology, which can further improve system performance. Finally, we present the physical implementations for the waferscale system with heterogeneous dies.

The Dynamic Heterogeneous Redundancy (DHR) architecture presents a novel approach to system design and organization, aiming to enhance system security by integrating dynamicity and heterogeneity into its structure. Despite its practical efficacy, the theoretical underpinnings elucidating the mechanisms through which DHR enhances security remain unestablished. This study endeavors to bridge this gap by conducting a theoretical analysis and modeling of the DHR architecture, focusing on its intrinsic characteristics and their implications for system security. Employing static game theory, our research uncovers the unique Nash equilibrium within DHR architecture. Expanding upon this mathematical framework, we delve into how factors such as dynamicity, heterogeneity, and failure rates influence these equilibria, subsequently shaping system security. To validate our findings, we conduct a case study involving a triply redundant DHR system and simulate the offense-defense interplay using the Adam optimization algorithm within boundedly rational static games. Our results affirm the variations in system security under diverse initial conditions and model states, thereby establishing a robust theoretical foundation for DHR architectures and laying the groundwork for their broader comprehension and application across various domains.

Abstract At present, attacks based on the vulnerability of the controller and flooding attacks still constitute a principal threat for hierarchical Software Defined Network (SDN), such as flow table tampering, malicious Application attacks, Distributed Denial of Service (DDoS) etc., due to the limitation against attacks based on known or unknown vulnerabilities for traditional cyber defence technology. Therefore, this study proposes an active defence architecture based on Mimic Defence (MD)–Mimic Hierarchical SDN Framework (MHSDN). Then endogenous security of MHSDN is theoretically analysed. Simultaneously, the attack surface measurement of MD is innovatively proposed, further improving the security and usability measurement standards of the MD system. Finally, to speed up detection and reduce defence cost of DDoS, this research proposes the Random Forest Feature Extract (RFFE) and tolerable switch migration. Simulation shows that RFFE has achieved a faster detection speed at the cost of less detection accuracy, and MHSDN can better improve the reliability of hierarchical SDN.

In SDN, the controller is the core and is responsible for processing all flow requests of the network switches. However, due to the sudden occurrence and unbalanced distribution of flows in the network, it is likely that some controllers suffer workload that is far heavier than their load capacity, which leads to the failure of the controller and further leads to the paralysis of the entire network. To solve this problem, we propose a dynamic flow redirection scheme (DFR) to prevent network crash. We describe the phenomenon of controller failure caused by numerous flow requests. The flow redirection is formalized as a multi-objective optimization problem and constrained by flow table and bandwidth. We prove that the problem is NP-hard. We solve this problem with the dynamic flow redirection approach (DFR). First, state detection module detects whether the current flow requests will exceed the controller load. The Flow Redirection Assignment Module then computes the redirect path for the redundant flow request. Finally, Rule Dispense issues the flow rules to the corresponding switches. Simulation results show that DFR reduces network latency and reduces the overload probability of controllers by at least 3 times.

Now, Convolutional Neural Network (CNN) has gained great popularity. Intensive computation and huge external data access amount are two challenged factors for the hardware acceleration. Besides these, the ability to deal with various CNN models is also challenged. At present, most of the proposed FPGA-based CNN accelerator either can only deal with specific CNN models or should be re-coded and re-download on the FPGA for the different CNN models. This would bring great trouble for the developers. In this paper, we designed a software-defined architecture to cope with different CNN models while keeping high throughput. The hardware can be programmed according to the requirement. Several techniques are proposed to optimize the performance of our accelerators. For the convolutional layer, we proposed the software-defined data reuse technique to ensure that all the parameters can be only loaded once during the computing phase. This will reduce large off-chip data access amount and the need for the memory and the need for the memory bandwidth. By using the sparse property of the input feature map, almost 80% weight parameters can be skipped to be loaded in the full-connected (FC) layer. Compared to the previous works, our software-defined accelerator has the highest flexibility while keeping relative high throughout. Besides this, our accelerator also has lower off-chip data access amount which has a great effect on the power consumption.

Regular expression matching plays an important role in network security. Regular expression matching is achieved by NFA and DFA. DFA is suitable for high-speed IDS due to its efficiency. However, the combined compilation of multiple rules containing “.*” may blow up in state and storage space. In this paper, we give an explanation to this problem from the prospective of information theory, and propose a multidimensional mathematical model focusing on the most serious state explosion. We divide redundant states into zero-dimensional ones and one-dimensional ones. The former are compressed by dimension, and the later are dynamically built. Theory proof illustrates that the space complexity of the model reaches the theoretical lower bound. Then we propose the multi-dimensional finite automata (MFA) based on the model. Experimental results show that, MFA reduces greatly the construction time, memory and matching time, compared with several typical state-of-the-arts DFA improved algorithms.