A novel data-driven simulation-based diagnostic model is proposed to realize automatic and practical testability analysis (TA) of analog circuits. With this model and the corresponding methods, sufficient faults can be handily injected into the circuit under test and then be simulated to construct the sample data. Using these data, a kernel density estimation on K-nearest neighbors classification algorithm and its leave-one-out cross-validation method are studied to evaluate the testability metrics. To handle the possible high false alarm caused by the faults that have similar samples with the fault-free case, two strategies are carried out by ignoring the faults in the ambiguity groups or/and using the posterior weights to determine the final classification results. Furthermore, a sample compression approach is proposed to reduce the computational cost. Experimental results show that more accurate and reasonable TA and verification can be achieved by comparing with the traditional testability models and the state-of-the-art classification methods. And the diagnostic application against a real circuit based on the simulation data can also reach a satisfactory level.

An empirical study is conducted to analyze the fault models of CMOS gates in VLSI. The mutation analysis methodology is used to ensure the simulation experiments are sufficient enough. For the primitive CMOS logic cells: inverter, 2-input NAND, NOR and XOR gates, a total of 335 mutant circuits are generated, simulated and analyzed. Comparing with the previous work, several new fault models are revealed, such as other-logic and the indetermination fault categorys sub-categories: 0-to-X, 1-to-X and other-to-X. Besides, the experimental results show that the classic static stuck-at fault cannot cover many practical defects in a circuit since it just averagely accounts for less than 15% of the total faults. Many other useful conclusions are drawn, which may benefit the related fault-based applications.