This work demonstrates a 12-bit SAR ADC using a machine-learning-based LLM-LMS calibration processor to estimate the capacitor mismatch in the background. Three techniques–Learning Rate Decay (LRD), Learning Rate Dynamic-Adjustment (LRDA) and Momentum–were used to enhance the convergence speed of SAR ADC calibration. The LRD technique accelerates the preliminary convergence by gradually reducing the learning rate. The LRDA technique dynamically changes the learning rate based on the magnitude of the gradient, allowing the algorithm to respond quickly to environmental changes and to make precise adjustments as the gradient decreases. The Momentum technique simulates inertia by incorporating the influence of previous updates, which accelerates convergence and minimizes oscillations. Together, these techniques successfully improve the convergence speed and overall performance of the SAR ADC calibration process. Monte Carlo simulation results show that the worst ENOB improves from 8.3 bits to 10.4 bits, after using the proposed LLM-LMS calibration.

This paper presents a 10-bit two-channel time-interleaved successive-approximation-register (SAR) analog-to-digital converter (ADC) to achieve a maximum sampling rate of 400 MHz in 90-nm CMOS. The channel-ADC incorporates a 2b/cycle-assisted SAR architecture to effectively speed up its operation speed. A new dynamic register is proposed to reduce the DAC control delay. To maintain small capacitor arrays, a multiple-reference C-DAC is applied to avoid using a tiny unit capacitance. This prototype ADC consumes a total power of 3 mW from a 1.2-V supply at 400-MS/s. Measured DNL and INL are -0.77/+1.2 LSB and -1/+1 LSB, respectively. The measured peak SNDR and SFDR are 51 dB and 62.3 dB, respectively. The measured ENOB is 8.2 bits, equivalent to a figure-of-merit of 25.5 fJ/conversion-step.

A 16-bit 1-MS/s SAR ADC was fabricated in 180nm digital CMOS. To maintain excellent linearity, a window capacitor calibration (WCC) scheme is proposed to estimate capacitor mismatch and obtain corrected bit weights. Different from prior calibration schemes, the WCC scheme can alleviate the offset and flicker noise effects on the calibration accuracy. The total input capacitance is only 4.8 pF. This ADC consumes a total power of 0.91 mW from a 1.8-V supply and occupies an active area of 0.276 mm2. After using the proposed WCC scheme, measured INL is improved from -103/+106 LSB to - 1.3/+1.7 LSB. Measured SFDR and SNDR are 105 dB and 83.8 dB, respectively. This prototype ADC achieves a Schreier FOM of 172 dB.

This paper presents a 16-bit successive approximation register analog-to-digital converter (ADC) achieving over-100 dB spurious-free dynamic range (SFDR). This ADC uses VCM-based and binary-window digital-to-analog converter (DAC) switching schemes to improve the signal-to-noise and distortion ratio (SNDR). Moreover, alevel-2capacitor swapping scheme is proposed to achieve superior DAC linearity by using two intrinsic true random number sequences. A prototype ADC is fabricated in 180 nm CMOS technology and occupies an active area of 0.53 mm2. At 1 MS/s, it consumes a total power of 1.05 mW from a supply of 1.8 V. The measured differential and integral nonlinearity are −0.65/+0.45 and −2.2/+2.1 least significant bit. With an input of 1 kHz, the measured SNDR and SFDR are 83 dB and 100 dB. The effective number of bits is 13.5, which is equivalent to a Schreier figure-of-merit of 169.8 dB.

This paper presents an energy-efficient 12-bit successive-approximation register (SAR) analog-to-digital converter (ADC) for biomedical and IoT applications. The synchronous SAR ADC operation was applied to meet the scaling of the sampling frequency for extending the battery life. The full capacitor swapping scheme was proposed to maintain both small input capacitance, better ADC linearity and SNDR. The 12-bit ADC was fabricated using a 180-nm CMOS technology. This prototype ADC consumes only 730 nW from a 0.7-V supply at 100-kS/s. With the Nyquist rate input, the measured SNDR and SFDR are 64.2 and 75 dB, respectively. The ENOB is maintained at 10.4 bits, equivalent to a figure-of-merit of 5.6 fJ/conversion-step. The sampling frequency can be scaled from 100 kHz to 1 kHz with ENOB > 10.4 bits.

This paper presents an 11-bit successive approximation register (SAR) analog-to-digital converter (ADC). The subranged-SAR ADC architecture is applied to achieve a sampling rate of 100 MHz. The proposed gain error compensation helps attenuate the gain error between coarse and fine ADCs. An up-then-down digital-to-analog converter (DAC) switching scheme is used to maintain a small common-mode variation for the fine comparator. To maintain a good spurious free dynamic range (SFDR), the capacitor-swapping scheme is applied in the DAC. The prototype ADC was implemented using a 65-nm CMOS technology. It consumes a total power of 2.4 mW from a 1.2-V supply. The measured peak signal-to-noise-and-distortion ratio and SFDR are 61.1 and 85 dB, respectively. The peak effective number of bits is 9.86, equivalent to a figure-of-merit of 25.8 fJ/conversion step.

This paper presents a metastability detection circuit to improve the bit-error-rate (BER) of analog-to-digital converters (ADCs) which use the asynchronous operation. In comparison with conventional metastability detectors (MDETs), the proposed replica-type MDET is more helpful to improve the BER with better immunity to process, voltage, and temperature (PVT) variations. The proposed MDET can effectively detect the metastability and output a flag signal for asynchronous ADC operation. To verify the proposed MDET circuit, a comparator is evaluated in a 90nm CMOS technology. The simulation results show that the proposed PVT-tracking MDET can maintain both speed and accuracy requirements for asynchronous ADCs.

This paper presents an energy-efficient 12-bit successive approximation (SA) register analog-to-digital converter (ADC) for high-performance sensor systems. The ADC uses a two-step decision digital-to-analog converter (DAC) switching scheme for improving the DAC linearity with small capacitor arrays. The scheme effectively eliminates the largest binary DAC middle-code transition glitch. The proposed switching scheme also tolerates DAC settling errors during SA. Avoiding unnecessary DAC switching error improves the spurious-free dynamic range (SFDR) and signal-to-noise-and-distortion ratio (SNDR). A reference-scaling binary capacitor DAC is used for improving the ADC energy efficiency without sacrificing production reliability. The implemented prototype in 0.11-μ CMOS occupies an active area of 0.097 mm2. At 1 MS/s, it consumes a total power of 24 μ from a 0.9 V supply. The measured differential nonlinearity and the integral nonlinearity are 0.4 least significant bit (LSB) and 0.7 LSB, respectively. Among 50 chips, the peak measured SNDR is 68.3 dB. The peak and the average of SFDR are 89 and 83.5 dB, respectively. The optimal effective number of bits is 11 bit at the Nyquist-rate input, which is equivalent to a figure of merit of 11.7 fJ/conversion-step.

This paper presents a digital-subranging (sub-R) analog-to-digital conversion (ADC) architecture to improve the operation speed of sub-R ADCs. Long latency between coarse and fine conversions will slow down the conventional sub-R ADCs. The proposed digital-sub-R uses digital circuits to implement the sub-R function and shorten this latency, thus benefits the CMOS scaling. Furthermore, the dynamic comparators are used to save more ADC power consumption. Their accuracy is improved by the proposed pseudodifferential offset calibration loop. The digital-sub-R also helps to reduce the dynamic offset of the fine comparators caused by the input common-mode variation. Fabricated using a 55-nm CMOS technology, the reported 8-bit 1-GS/s ADC consumes only 16 mW from a 1.2 V supply. Measured signal-to-noise ratio (SNR) and spurious free dynamic range (SFDR) are 46 and 55 dB, respectively. Measured effective number of bits (ENOB) is seven bits at 10-MHz input frequency. At Nyquist input, the ENOB performance of 6.3 bits is still maintained. Its figure-of-merit is 197-fJ/conversion-step.

This paper presents a perturbation-based gain and nonlinearity background calibration scheme for high-resolution pipelined analog-to-digital converters (ADCs). Two uncorrelated pseudo-random sequences are used to inject a perturbation signal into the pipeline stages and then estimate the linearity of multiplying digital-to-analog converters (MDACs). The gain and linearity errors are corrected to achieve high-resolution performance. A 14-bit pipelined ADC is simulated to verify the proposed calibration scheme. The SNDR is improved from 45 dB to 80 dB. The simulated SFDR is over 99 dB to show the linearity improvement.

The binary-window capacitor switching algorithm is proposed for a binary-weighted capacitor array successive approximation register (SAR) analog-to-digital converter (ADC). It eliminates the middle-code transition glitch to improve ADC linearity. The swapping binary-window (SBW) DAC switching technique, which combines the capacitor swapping and the binary-window switching, further improves both linearity and signal-to-noise ratio (SNR). It can effectively reduce the total capacitance to approach a noise-limited design criterion, achieving better energy-efficiency. The static linearity improvements are shown with the integral non-linearity (INL) reducing by a factor of two due to the utilization of the SBW technique.