In a board level design with boundary scan, an interconnect is testable if it can be controlled and observed through the scan chain(s). One or more activated drivers can drive a net to the desired logic state, and the receiver(s) can observe the state of that net. To select driver(s) and receiver(s) for a testable net, associated control cell(s) has to be programmed with proper value(s). A conflict arises when a control cell value programmed for one net is different from the value previously programmed for another net. A driver selection algorithm is presented here to resolve such a conflict.

A hardware accelerator for the maze routing problem is developed. This accelerator consists of three three-stage pipelines. Banked memory is used to avoid memory read/write conflicts and obtain maximum efficiency. The design is compared to other proposed designs. Unlike other proposed hardware solutions for this problem, this design does not require an increase in the number of processors as the problem size increases.>

A hardware accelerator for the maze routing problem is developed. This accelerator consists of three 3 stage pipelines. Banked memory is used to avoid memory read/write conflicts and obtain maximum efficiency.

The increasing difficulties in testing large logic networks have generated the need for designing logic networks for testability. Computer algorithms for designing diagnosable metal oxide semiconductor (MOS) networks with and without fan-in, fan-out constraints were described in previous papers by the authors. In this two-part series, we discuss the testing of these designed networks.

This paper discusses the main shortcomings of existing software test pattern generation systems and describes the development of a new system. The new system will be developed in two phases. The first phase is called the scan-in/scan-out test generation sub-system. This sub-system will be used for testing designs which have 100% scan-in/scan-out (reading or writing of every register from external world is possible). The second phase will include the development of efficient general functional models. The test generation system to be developed in the first phase will be updated to incorporate the capability of handling such models. The functional models include general-combinational, register, counter, ROM, RAM, and microprocessor. In this paper, only, an outline of some of the distinct features of the system will be described.

Metal-oxide-semiconductor (MOS) logic elements offer advantages over bipolar logic elements, such as smaller size, complexity, and power consumption, as well as more flexibility and versatility. Since MOS is playing a major role in large-scale integration (LSI), synthesis of MOS networks with a large number of variables is very important.