This article presents an effective method to enhance the RF self-interference cancellation (SIC) at higher-order stages through the Spectral-Shaper circuit. The mathematical model of the Spectral-Shaper circuit, along with its simulation and experimental results, is presented. The generic architecture for scaling the canceller stages to higher orders is described. The proposed technique is validated through an experimental prototype built on a printed circuit board at 2.45 GHz, using commercially available off-the-shelf surface-mount components. The prototype comprises two-stages: in the first stage, a variable attenuator and a phase shifter are employed, achieving 22.5 dB of cancellation; the second stage employs a Spectral-Shaper circuit and provides an additional 32.9 dB of cancellation improvement. The prototype canceller was able to suppress a +27 dBm transmit signal by 73.6 dB over a 20-MHz channel bandwidth, exclusively in the RF domain. The canceller IP1dB is +30.1dBm, and the IIP3 at the transmit path and the canceller stage are +53.9 dBm and +42.3 dBm, respectively.

This paper discusses the design automation and optimization of a digitally tunable reflective type lumped element phase shifter. The phase shifter is based on a branch-line coupler built using capacitors and inductors. The reflective load to this coupler is provided using a digitally tunable capacitor bank. To test the automation algorithm, a 5-bit 180° reflective type phase shifter (RTPS) at 3 GHz was designed using TSMC 65nm CMOS technology. The RMS phase error of this RTPS is less than 3°over a bandwidth of 240 MHz (2.76 GHz - 3 GHz), with a minimum value of 0.3° at 3 GHz. The insertion loss is about 7.3 3 dB. The runtime of the optimization code is about 120-150±seconds on an i9 system with 32 GB memory.

Two 28GHz mm-wave quadrature voltage-controlled oscillator designs in a 45nm bulk CMOS process are reported in this work. The first topology uses two VCOs coupled with each other using cascode devices. The second topology uses a single VCO followed by a Lange Coupler to give quadrature phase outputs. This comparative study shows that the latter exhibits better phase noise and tuning range with respect to the former. Post-layout EM simulations of the Lange Coupler QVCO predict an improvement of 4-6 dB in phase noise over the Cascode Injected QVCO, across all bit configurations. The total dc power consumption of this Lange coupled QVCO with two buffers is 20 mW when running at a power supply of 1.1V.

In this paper, the design and analysis of a 28 GHz CMOS Low noise differential amplifier is discussed. A current reuse technique is used to minimize power consumption by stacking two common source amplifiers. The proposed LNA is designed in a 65nm RF CMOS process to achieve an output matched voltage gain of 18.5 dB and minimum Noise figure(NF) of 4.6 dB. The LNA consumes 10mW from a 1.2 V power supply and exhibits an input-referred 1dB compression point of -16.1 dBm. The LNA is designed using transmission lines, inductors, high-Q capacitors, and a transformer, and occupies a total area of only 0.33 mm2.

An ultralow-power low-noise analog front end (AFE) for ECG signal acquisition is demonstrated. The key to its performance is a multifrequency chopping technique that helps to significantly reduce power consumption by frequencydivision multiplexing of two channels in a single low-noise instrumentation amplifier (IA). A complete two-channel AFE, chopped at frequencies of 4 and 8 kHz, is implemented in a 0.13-μm CMOS technology from United Microelectronics Corporation. A current-reuse technique is employed in the first stage of the IA to achieve area savings and improve interchannel isolation. Experimental results show that the front end achieves an input-referred noise voltage density of 130 nV/rtHz while consuming current of 360 nA per channel from a 1.2-V power supply. The 1/f noise corner of the system is around 10 Hz, and the measured common-mode rejection ratio (CMRR) is 98 dB.

Millimeter-wave voltage-controlled oscillators (VCOs) require small tank inductors due to large parasitic capacitances contributed by MOS switches and cross-coupled pair. This significantly increases the effect of routing inductance on the uniformity of tuning range. In this brief, mathematical analysis has been carried out to explain tuning behavior in the presence of routing inductance. A symmetrically distributed SWCB is proposed, which provides a uniform discrete tuning range, leading to a 3.6× reduction in the varactor size compared to traditional implementations. Two VCOs with different tank structures have been implemented in a Texas Instruments proprietary 130-nm BiCMOS technology. Measurement results show an oscillation frequency of 23.5 GHz with a phase noise performance of -111 dBc/Hz at 1-MHz offset from the carrier, leading to an figure of merit of -181 dBc/Hz. A layout structure that enhances continuous tuning range is validated on a third fabricated VCO through a measured 300% improvement in continuous tuning range.

Time selective sampling is capable of eliminating strong interference signals without requiring a high linearity receiver front-end. This can be used to implement a full-duplex transceiver front-end by sampling the weak received signal at the zero-crossings of the strong transmitted signal. In this work, we propose a circuit technique to directly sample the received RF signal at the antenna port by exploiting implicit voltage-to-delay conversion occurring in a full-duplex system. The sampler is implemented in a 65 nm CMOS process, and simulation results show a sensitivity of -67 dBm in the presence of a +5.5 dBm Tx signal. The received signal has a 10 MHz bandwidth, and the overall receiver consumes 33.2 mW from a 1.2 V power supply.

A low phase noise Ku-band VCO fabricated in 130 nm BiCMOS technology is presented. The prototype 12.2–13.1 GHz VCO achieves a measured phase noise of −120.6 dBc/Hz at 1 MHz offset. The VCO core consumes a power of 17.7 mW and attains a Figure of Merit (FOM) of 190. Temperature-compensation techniques are applied to MOSFET bias, switched capacitor bank bias and LDO voltages to reduce VCO frequency drift down to 7.6 MHz over a temperature range of −40°C to 125°C (578.4 ppm).

A BJT based cross-coupled pair limits the maximum achievable oscillation frequency of LC-VCOs due to high parasitic capacitance in mature Si/SiGe technologies. In this work, class-C biasing is exploited to reduce cross-coupled pair parasitics, helping to enhance oscillation frequency without compromising phase noise performance. A design methodology is suggested to optimize cross-coupled pair parasitics with better phase noise performance. A dual-core architecture helps to achieve further phase noise improvement. The VCO is designed and fabricated in a 130nm BiCMOS technology using a bipolar cross-coupled pair. It achieves a maximum oscillation frequency of 27.2GHz and exhibits a measured phase noise performance of -110.7dBc/Hz @ 1MHz offset from the carrier, with an FoM of 181dBc/Hz.

In this brief, a low phase noise Ku-band voltage-controlled oscillator (VCO) fabricated in a 130-nm BiCMOS process is presented. The phase noise mechanism of the switched-capacitor bank is analyzed, an optimum bank design to reduce phase noise is proposed, and a tradeoff with tuning range is discussed. The prototype 12.2–13.1-GHz VCO achieves a measured phase noise of −120.6 dBc/Hz at 1-MHz offset when running at 12.67 GHz. The VCO core consumes a power of 17.7 mW and attains a figure of merit of 190.

The expression for phase noise of a bipolar class-C voltage controlled oscillator (VCO) with an ideal delay in the oscillator loop is derived in this paper. The impact of internal device parasitics is then quantified and supported with circuit simulation results. A bipolar class-C VCO is fabricated in a 130-nm BiCMOS technology to validate the analytical predictions. It exhibits a phase noise performance of -112.2 dBc/Hz at 1-MHz offset when running at 19.2 GHz. The tuning range is 7%, and the overall FoM and FoMT are 180.4 dBc/Hz and 177.3 dBc/Hz, respectively.

The fundamental problem in the design of a fullduplex radio is the cancellation of the self-interference (SI) signal generated by the transmitter. Current techniques for suppressing SI rely on generating a copy of the SI signal and subtracting it partly in the radio frequency (RF) and digital domains. A critical step in replicating the self-interference is the estimation of the multipath channel through which the transmitted signal propagates to the antenna. Since there is no prior model on the number of multipath reflections, current techniques assume a tap delay line filter (in the RF and digital domain) with a large number of taps, and estimate the taps in the analog and the digital domain. In this paper, using a linearization technique, we show that the self-interference channel in an indoor environment can be effectively modeled as H(f ) = C0- C1f in the frequency domain. Thus, the effective self-interference channel can be represented by two parameters C0and C1, irrespective of the multipath environment. We also provide experimental evidence to verify the above channel model and propose novel low-complexity designs for self-interference cancellation.

A reconfigurable dual-band radio frequency power amplifier topology (PA) is proposed in this work. The supply bias inductor is shared between two PAs that are designed to operate in two different frequency bands. The primary advantage is significant reduction in silicon area, without compromising on RF performance and power efficiency. To validate the proposed technique, a PA for the LTE cellular system is designed and simulated in a UMC130nm CMOS process. The PA can be configured to operate in the 900MHz or 1.8GHz frequency bands. In both bands, the PA is capable of delivering modulated output power of 5dBm to a differential 100Ω load while meeting the stringent linearity requirements of the LTE standard. In the 900MHz a d 1.8GHz bands, the worst-case adjacent channel power rejection (ACPR) performances are -48dBc and -44.5dBc respectively.

Design of tunable multi-band time delay elements based on frequency translation is presented. The proposed topology exhibits time delay of multiple periods of the RF carrier. Two possible implementations of the proposed idea are presented and simulation results are shown for one such implementation. The implemented circuit exhibits an envelope delay of 2.5 ns with the RF carrier delay tunable from 0° to 360° in 45° steps in the 2.4 GHz ISM band.

Digital circuits exhibiting rail-to-rail voltage swings display large spreads in current consumption and delay over variations in process, voltage and temperature (PVT). A circuit technique is proposed to enable optimal current consumption and low delay distribution in high frequency digital circuits. A typical RF application is chosen at 5 GHz frequency, for which a divider is designed and simulated in a UMC 130nm CMOS process. With the proposed scheme, the circuit shows up to 52% reduction in current, while the relative variation in delay over PVT reduces by 70%.

Ground-bounce due to bond wire inductance is a well known problem in Radio-Frequency (RF) Integrated Circuits. In this paper we propose the use of series resonance with an extra bond wire to substantially reduce ground-bounce effects in narrowband RF front-ends. Instability caused by the ground bond wire is also tackled. Impedance balancing of output stage to null ground-bounce due to other on-chip circuitry is discussed. The proposed techniques are applied to the design of a power amplifier (PA) for 2.5GHz applications and detailed simulations are performed to support the same.

Shunt and series-coupling techniques for quadrature generation are applied to CMOS relaxation oscillators. The 2.4GHz quadrature oscillators are designed and simulated in a UMC 0.18µm CMOS process. The shunt-coupled oscillator consumes a current of 12mA from a supply of 1.8V and achieves a phase noise of −99.4dBc/Hz @ 1MHz offset. The series-coupled oscillator consumes a current of 16mA from the 1.8V supply and achieves a phase noise of −98.3dBc/Hz @ 1MHz offset. For a systematic mismatch of 1%, the quadrature phase error of the shunt-coupled and series-coupled circuits are 0.55° and 0.1° respectively.

A delay generation technique applied to loop-bandwidth enhancement of frequency synthesizers is proposed for faster switching. PMOS transistors are used to provide large resistances and a diode-connected PMOS device generates the switch gate-bias voltage to reduce delay variations over process. An integer-N PLL employing the above technique for bandwidth enhancement is designed and simulated at 2.4GHz. It has a phase noise of -123dBc/Hz @ 1MHz offset. The lock time is 40mus, and the tuning range is 200MHz

A fully integrated 5-6GHz differential VCO derived from the classical Clapp topology is presented in 180nm CMOS. The Clapp architecture and its characteristics are reviewed, and the location of critical portions of the circuit such as the LC-tank and varactors is discussed. The use of a Clapp VCO topology allows a larger voltage swing, which improves spectral purity and phase noise. The use of a symmetrical inductor for differential operation results in a higher Q with lower area, while providing common-mode noise rejection. The VCO achieves a simulated phase noise of -98dBc/Hz @ 100kHz & -123.1dBc/Hz @ 1MHz offsets, and draws 5mA from a 1.8V power supply. A high tuning range of 18% and FOM of 189dBc/Hz are reported. Finally, system-level simulations of a frequency synthesizer for the IEEE 802.11a bands using the Clapp VCO are presented