As focused ion beam (FIB) technology advances and invasive attack methods evolve, tilted FIB and rerouting attacks pose serious threats to chip security. Existing single-layer active shields exhibit inherent limitations in defending against these advanced invasive attacks. This paper presents the X-Matrix Shield, a dual-layer structure that fortifies integrated circuits against sophisticated physical tampering. This research establishes a novel information theory-based evaluation framework with quantifiable direction entropy metrics. Additionally, the work develops an improved artificial fish-swarm algorithm (DAFSA) to generate optimized 3D-interlaced protection paths. X-Matrix Shield can be directly integrated into the standard EDA layout flow, enabling security-aware physical design co-optimization. When implemented in 55 nm standard process technology, the X-Matrix Shield achieves a quality metric of $\mathbf{1. 9 9}$. GDS3D simulations of protected AES modules further confirm the shield’s effectiveness against advanced physical attacks compared to single-layer protection.

This article presents a novel readout circuit for the resistive tactile sensor array. Based on the 2-D scanning mechanism, a crosstalk suppression technique is proposed by combining the correlated double sampling (CDS) and zero potential method (ZPM). The output of the same sensor under different bias conditions is captured twice and amplified by a channel-parallel fully differential gain stage, performing analogous subtraction. To achieve nonuniformity compensation, the current injected into the readout channel is adjusted by the channel-parallel digital-to-analog converter (DAC). A successive approximation register (SAR) analog-to-digital converter (ADC) performs quantization, and the chip can be used as a serial peripheral interface (SPI) slave to update register values for gain configuration, power consumption control, and nonuniformity compensation. The 180-nm CMOS prototype chip occupies an area of$4.8~\text {mm}^{2}$and consumes$285~\mu $W. In order to validate the design, a tactile sensing system is built, using the readout circuit along with a$10\times 10$flexible sensor array. With the techniques proposed in this article, the readout error of the sensors in array is less than 0.3‰.

This article presents a low noise and wide linear dynamic 20-channel analog front-end (AFE) array for frequency-modulated continuous-wave (FMCW) light detection and ranging (LiDAR) system. Each channel of the AFE array mainly consists of a shunt feedback transimpedance amplifier (SF-TIA) with a dc cancellation loop (DCL), a post amplifier, and an output buffer. The DCL is proposed to eliminate the dc current, comprising the dc current sunk to ground (dc-STG) and the dc current sourced from power supply (dc-SFP). In addition, the post amplifier, cascaded with an operational transconductance amplifier (OTA) and an SF-TIA, is proposed to decouple the relationship between gain and output common voltage, achieving both large gain and large output swing. Furthermore, the equalization technique is adopted to expand the bandwidth of the AFE array. The AFE array was implemented and fabricated in a 0.18-$\mu \text{m}$CMOS technology. Measurement results show that the AFE array achieves the maximum transimpedance gain of 107 dB and eliminates the dc current between −150 and$250 ~\mu \text{A}$. With the maximum transimpedance gain, the measured bandwidth, the equivalent input-referred rms noise current, and the signal-to-crosstalk ratio (SCR) between adjacent channels are 165 MHz, 29.4 nArms, and −33.9 dB, respectively. The AFE array also achieves a linear dynamic range (DR) of 66 dB and the area of each channel is approximately equal to$0.16\times1.3$mm2.

Active-RC continuous-time Delta-Sigma modulators (CTDSMs) are an attractive solution for power-efficient and precise analog-to-digital conversion. Multi-bit CTDSMs offer reduced jitter sensitivity and lower over-sampling ratios, which make them suitable for wideband applications compared to their single-bit counterparts. However, they suffer from the problem of element mismatches in their digital-to-analog converters (DACs). On the other hand, in state-of-the-art CTDSMs, the DACs can consume a significant percentage of the overall power. In this manuscript, we present an active-RC CTDSM with a novel 5-level highly linear switched-capacitor (SC) DAC, which reduces power consumption through charge recycling. Splitting a DAC capacitor into two halves helps avoid harmonic distortions caused by signal-dependent timing of DAC pulses. A 10-MHz bandwidth modulator with an 800-MHz sampling frequency (fs) is designed in a 65-nm CMOS technology. Transistor-level simulations show that it achieves 75.9 dB SNDR and 88.8 dB SFDR while consuming 1.28 mW from a 1.2-V supply. Despite the DAC being of the SC type, the modulator achieves high aliasing rejection ratios of 68.8 dB and 65.9 dB at fsand 2fs, respectively.

This brief presents a low-complexity hybrid readout architecture that can extract both timing and amplitude information of the return pulse concurrently for a light detection and ranging radar (Lidar) receiver. To reconstruct the short return pulse, the core circuit of one sampling and storage array with an embedded time-to-digital converter (SSA-TDC) is proposed. Instead of relying on the conventional power-hungry high-speed ADC, it selectively samples the interested return pulse with high speed and stores the voltages for later quantization in the long idle interval. In the preceding stage of the SSA-TDC, the analog front-end circuit cascaded of a narrow-bandwidth transimpedance amplifier, a voltage amplifier, and an equalizer circuit is included. The prototype chip of the eight readout channels is designed and fabricated with the 0.18-μm CMOS process. The active circuit occupies an area of 1200 μm × 2100 μm, and the power consumption of one single channel is 45 mW with 3.3-V supply. The proposed SSA-TDC has achieved a dynamic error of 180 ps in the experimental study.