International audience

The quest for reliable testing of analogue and mixed-signal circuits remains a cornerstone in the advancement of integrated circuit technology, driving innovation in high-stakes areas such as aerospace and automotive systems. The continuous nature of the signals and the variability of the components make the task both time consuming and difficult to automate. This work presents a general methodology to detect parametric faults in analogue circuits using machine learning models combined with Monte Carlo simulations, advanced signal transformations and optimal classifier selection. The proposed framework is adaptable to different circuit architectures, as demonstrated by simulations of RLC bandpass filters and Sallen-Key filters. In particular, our approach incorporates new metrics that balance classification accuracy with implementation complexity and computational efficiency, providing a scalable solution adapted for automation and integration into an embedded test environment.

Finding critical nodes and devices inside a circuit is important to have a reliable and safe circuit. It is also a necessary information to successfully solve a failure analysis. Besides, this is a difficult task when dealing with analog and mixed signal circuits for safety applications. For complex designs, the list of signals that influences a selected output is not easy to be deduced. This paper proposes a solution to meet these needs. It is a method that is potentially opened to a broader application domain than failure analysis. The obtained results are encouraging and show the advantages of such approach.

The failure analysis in analog and mixed signal products is mainly based on measurements performed in the laboratory without any simulation support. The fault simulators for analog circuits are starting to be available but are not designed for these needs. This work describes the integration of the simulation into the normal failure analysis flow using test software developed for analog fault simulation. We propose an innovative iterative flow for diagnosis of analog IPs and products. The results show how inserting such tools in the fault isolation step, we speed up the whole analysis process, allowing the diagnosis for analog and mixed-signal circuits.

The disruptive potential of the IEEE 1687 standard does not come from a single innovation, but rather from its capacity of providing a unified framework where heterogeneous approaches can co-exist and interact. In this Special Session, we will present the complementary research activities performed in the TIMA laboratory covering different aspects of the standard (Mixed-Signal instrument testing, Embedded Aging Monitors and Test Access Securization), and their coordination thanks to the Manager-for SoC Test (MAST) software environment.

This paper presents the construction of a control loop for the concealment of defective pixels in an image or an image sensor. The proposed control loop is based on defective pixel detection methods, and the concealment of the detected defective pixels. Two detection algorithms have been used in the process. The first is based on distance and the second on the evaluation and analysis of local dispersion parameters of the pixel blocks in the input image. The concealment process uses the median filter. The proposed control loop takes as input an image and a defective pixel number threshold into an image, and outputs the final corrected image, after passing through defective pixel detection and correction phases if necessary.

This paper presents an online and integrated solution for diagnosis and healing of the image sensors based on a defective pixel detection and concealment method. The proposed defective pixel detection method is based on the evaluation and analysis of the median, range and other local dispersion parameters of the pixel blocks in the images taken by the to-be-tested image sensor. Once a defective pixel is detected, the concealment process uses a median filter, which consists of the substitution of the defective value by the median value of the pixel block. For an error detected in the image sensor, a diagnostic process can be used to determine the origin of the problem. The global detection and concealment process was implemented on an FPGA platform to evaluate the computational complexity and to confirm the feasibility of integrating the proposed solutions in image sensors.

This paper presents imager self-healing method based on detection and correction of defective pixels in the produced image file. The proposed method uses a neighborhood analysis with simple arithmetic operations including distance between the to-be-tested pixel and its neighbor pixels. A 2-dimensional 3 by 3 gray-scale image matrix around the to-be-tested pixel is used to estimate an expected pixel value and a weighted average. This average value is used as an adaptive threshold of the difference value between expected and actual pixel values. The performances in terms of sensibility, specificity, predictive values, and phi-coefficient of the produced results on a set of 144 distorted images (24 references images x 6 distortion types), are compared to another dead pixel detection methods performances. Experimental results demonstrated that our proposal produces the best results.

In this article, we apply different machine learning (ML) techniques for building objective models, that permit to automatically assess the image quality in agreement with human visual perception. The six ML methods proposed are discriminant analysis, k-nearest neighbors, artificial neural network, non-linear regression, decision tree and fuzzy logic. Both the stability and the robustness of designed models are evaluated by using Monte-Carlo cross-validation approach (MCCV). The simulation results demonstrate that fuzzy logic model provides the best prediction accuracy.

This paper presents an Embedded Test Instrument (ETI) for the estimation of the High Frequency (HF) jitter of an observed clock signal. The ETI uses a second reference clock for under-sampling the observed signal similar to previous approaches. However, the analysis of the test response does not require the construction of the Cumulative Distributed Function (CDF) of the jitter as in previous approaches. Instead, the HF jitter of the input observed signal is transformed at the output of the ETI into a digital value that corresponds to a number of unwanted signal transitions. We demonstrate in this paper that the transfer function of the ETI defined by the ratio of the number of unwanted signal transitions and the input HF jitter is linear. This property leads to a simple circuit implementation. The linearity of the ETI is demonstrated firstly by behavioral simulation, using a theoretical model of the output of the under-sampling process, and secondly by transistor-level simulation using the 65 nm CMOS bulk technology by ST Microelectronics. We also present experimental measurements that have been carried out using an FPGA-based test platform to validate the linearity of the transfer function in the presence of non-idealities that can affect the ETI. Finally, we demonstrate the exploitation of the ETI within Systems-on-Chip (SoCs) produced in highvolume by ST Microelectronics.

Most of Wireless Sensor Networks are deployed to monitor a set of targets over a specified area. The lifetime of such a network is defined as the time duration from the network deployment till the time when one target is no longer covered. Thus, this lifetime is limited by the energy resource of sensor nodes. In order to maximize the lifetime of the network, only a subset of nodes capable of covering all targets are activated at a time while the others are put in sleep mode to save their energy. When an active sensor fails, a recovery procedure should be executed to keep all targets covered. In this paper we propose a new self-healing method for network reconfiguration in case of failure of an active node. Simulation results show that this method increases the network dependability by reducing the network unavailability time up to 90 % % compared to the dynamic maintenance for networks with more than 200 sensor nodes of sensing range equals to 10, uniformly deployed over a 50 × 50 square to cover 50 targets also uniformly deployed over the same area.

We propose a post-fabrication calibration technique for RF circuits that is performed during production testing with minimum extra cost. Calibration is enabled by equipping the circuit with tuning knobs and sensors. Optimal tuning knob identification is achieved in one-shot based on a single test step that involves measuring the sensor outputs once. For this purpose, we rely on variation-aware sensors which provide measurements that remain invariant under tuning knob changes. As an auxiliary benefit, the variation-aware sensors are non-intrusive and totally transparent to the circuit. The technique is demonstrated on a 65nm RF power amplifier.

In the context of mission-critical, safety-critical, and remote-controlled applications, it is required to equip systems with self-adapting capabilities. Adaptation is required in post-manufacturing to correct yield loss and achieve zero defective parts-per-million as well as during normal operation to account for different application scenarios and for varying environmental conditions. A self-adaptive system must be capable of providing the required high performances after manufacturing and throughout its normal operation regardless the application scenario wherein it is deployed and despite the varying environmental conditions. In this paper, we describe a generic post-manufacturing self-adaptation technique for RF circuits as well as concurrent self-adaptation techniques for a safety-critical medical sensor for glaucoma diagnosis and for a NFC system which is very sensitive to the environment in which it operates.

In this research work, a non-linear regression-based prediction method is incorporated into a digital video decoder loop to monitor the visual quality of videos during the decoding process. Considering well-known video quality metrics, a Video Quality Monitoring Tool (VQMT) has been developed for efficient re-use in a variety of video processing tasks. The idea is based on the fact that when human observers rate video quality, they consider reference aspects such as Noise affecting the video or Neatness of images. In addition, transmission errors such as packet loss rate may impact video quality as well. Therefore, defining a Regression model between each one of these reference aspects and the Mean Opinion Score (MOS) provided by human observers can lead to an automatic way to supervise video decoding quality. Promising results have been achieved using a Non-linear Regression (NLR) method together with fundamental video quality metrics namely PLR (Packet Loss Rate), PSNR (Peak Signal to Noise Ratio), the SI (Spatial Index) and the TI (Temporal Index).

This work presents an approach for including energy consumption information in high-level modeling of active linear electrical circuits. The method introduced here proposes to start from a description of the system at a high-level of abstraction (transfer function or state space model) and refine it in order to generate the electrical circuit corresponding, in the form of a SPICE netlist, for example. The following steps of the proposed approach automatically extract the state space representation corresponding to this circuit. During the state space representation extraction, the information needed to find the power consumption is regarded as an output of the state space model. These outputs allow an instantaneous monitoring of the power consumption of the system at a high-level of abstraction. SystemC AMS has been used to model and simulate the examples presented in this paper.

Ordering of analog/RF tests is important for the identification of redundant tests. Most methods for test ordering are based on a representative set of defective devices. However, at the beginning of production testing, there is little or no data on defective devices. Obtaining this data through defect and fault simulation is unrealistic for most advanced analog/RF devices. In this work, we will present a method for analog/RF test ordering that uses only data from a small set of functional circuits. A statistical model of the device under test is constructed from this data. This model is next used for sampling a large number of virtual circuits which will also include defective ones. These virtual defective circuits are then used for ordering analog/RF tests using feature selection techniques. Experimental results for an IBM RF front-end have demonstrated the validity of this technique for test grading and compaction.

Timing synchronization represents a major challenge in carrying out highly efficient ultra-wideband (UWB) communications. The Delay-Locked Loop (DLL) method is widely proposed to maintain the satisfactory synchronization and reduce timing error. In this paper, we modify the structure of DLL, using a novel control strategy in the communication systems, called Internal Model Control (IMC), which is composed of an inverse model (control model) connected in series with the DLL system and a forward model (system model) connected in parallel with the DLL system, this structure has a good performance of overcoming disturbance and deviations of model parameters. Next, we apply the Least-Squares (LS) estimation algorithm method in order to determine the optimal coefficients for the system and control models. Simulation results confirm that the timing estimation performance is improved by using the proposed DLL scheme.

This work presents an approach for modeling a CMOS image sensor (CIS) by using the SystemC AMS analog and mixed-signal extension to the SystemC hardware description language 1666 IEEE standard. The advantage of developing such a model resides in the possibility of performing an early validation of the response of the image sensor to the input light. The parameterized model can model many optical and electrical effects at a high level of abstraction. The sensor response to the light and to its control signals can be rapidly simulated for checking the compliancy to the sensor specifications. SystemC AMS can model complex heterogeneous systems at different levels of abstraction using different models of computation (MoCs). The model uses the timed data flow (TDF) MoC of SystemC AMS. Simulation results are shown and future works are forecasted to enrich the accuracy of the sensor model by adding noise sources and non-linearities. The overall image acquisition platform will then be, in a near future, validated by integrating the SystemC AMS model inside a SystemC TLM virtual platform.

This paper presents a new approach for controlling power consumption in RF devices. The approach is based on the definition of application-dependent performance modes for power hungry RF circuits and a logical control strategy that adjusts the power supply of each circuit to the mode required by the application. The control strategy uses embedded sensors, a recursive parameter identification approach and regression models for performance prediction, while demanding minimum embedded resources for computation. The control strategy is robust with respect to circuit parametric deviations due to the manufacturing process or ageing mechanisms. The strategy is illustrated for the case of an RF LNA using envelope detectors as embedded sensors. Simulation results of the control strategy at the transistor-level illustrate the energy savings that can be obtained for an example application.

This paper presents an approach for ordering analog specification (or functional) tests that is based on a statistical estimation of parametric defect level. A statistical model of n specification tests is obtained by applying a density estimation technique to a small sample of data (obtained from the initial phase of production testing or through Monte-Carlo simulation of the design). The statistical model is next sampled to generate a large population of synthetic devices from which specification tests can be ordered according to their impact on defect level by means of feature selection techniques. An optimal order can be obtained using the Branch and Bound method when n is relatively low. However, for larger values of n, heuristic methods such as genetic algorithms and floating search must be used which do not guarantee an optimal order. Since the value of n can reach several hundreds for advanced analog integrated devices, we have studied a heuristic algorithm that considers combinations of subsets of the overall test set. These subsets are easier to model and to order and a heuristic approach is used to form an overall order. This test ordering approach is evaluated for different artificial and experimental case-studies, including a fully differential operational amplifier. These case-studies are simple enough so that it is possible to compare the results obtained with the algorithm with an expected reference order.

This paper introduces a new method combining low frequency actuation signal as test stimuli and envelope detection on the RF (radiofrequency) output signal to provide a low cost mean for offline as well as for online testing of RF MEMS switches. The study includes the modelling of RF MEMS switches as well as some ideas how to test online and diagnose their functionality. The proposed approach uses the principle of alternate test that replaces conventional specification-based testing procedures, which require sophisticated test equipment and are time consuming. The basic idea is to use the actuation signal as a low frequency online test stimuli to the RF device. The low frequency characteristics measured from the envelope of component response are utilized in a regression process to predict the RF conventional specifications parameters like s-parameters. In the context of our online testing scheme, on and off transition time estimated from the output low frequency envelope are used as test metrics and are concurrently updated using recursive algorithms. Preliminary validation results obtained on a capacitive RF switch are very encouraging.

This paper introduces a computer-aided-test platform that has been developed for the evaluation of test techniques for analogue and mixed-signal circuits. The CAT platform, integrated in the Cadence design framework environment, includes tools for fault simulation, test generation and test optimization for these types of circuits. Fault modeling and fault injection are simulator independent, which makes this approach flexible with respect to past approaches. In this paper, the use of this platform is illustrated for test optimization for the case of a fully differential amplifier. Test limits are set using a statistical circuit performance analysis that accounts for process deviations. Test metrics are estimated using this analysis. Specification-based tests are next optimized in terms of their capability of detecting catastrophic faults

This paper presents an implementation of on-line testing techniques for the case of a decimation filter. The decimation filter is used in a /spl Sigma//spl Delta/ analogue-to-digital converter that is in turn used in a built-in-self-test (BIST) circuitry for mixed-signal core testing. Thus, the filter itself must be self-testable. Three different one-line self-test techniques are studied and compared for a 0.18 /spl mu/m CMOS technology. The first one uses a non-concurrent structural test technique and the others are both based on semi-concurrent test methodologies. In all cases, the on-line test circuitry is automatically synthesized and exploits the idle time of the functional units to apply either a structural or a functional test.

The concurrent fault detection methods are generally based either explicitly or implicitly, on the use of redundancy. This paper presents a novel methodology for concurrent fault detection in linear digital systems. The basic principle of approach is the use of implicit analytical redundancy relations, i.e. relations between the measurement available variables. The robustness requirement of the redundancy relations guarantees a maximal sensitivity of the concurrent detector against fault and minimal sensitivity, towards noise. Techniques for designing fault detection circuitry using optimal redundancy relations are discussed. Error detection capabilities of the scheme proposed in this work are efficient for a very large class of linear digital signal processor. The test circuit obtained for concurrent fault detector implementation is still very reasonable.

A set of tools is described, allowing one to compute random testability measurement for combinational circuits, based on a black box worst case hypothesis. These tools provide enough information to allow circuit modification, in order to meet a prescribed testability value. The efficiency of these tools is due to the use of a statistical method combined with formal proof mechanisms. The random testability of the complete ISCAS benchmark of combinational circuits is computed. For the least testable circuits, a few modifications, guided by the testability measurements, are shown to be sufficient to make them randomly testable.>