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Achille Peternier

dblp:36/3217 · DBLP profile ↗
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13ranked-venue papers
6as first author
1since 2021 · last 2021
0000-0001-9794-2392ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 6 · 3 first-authorGraphics, computer vision, multimedia, augmented reality and games · 3 · 2 first-authorSoftware engineering, systems software and programming languages · 2 · 1 first-author · 1 since 2021Artificial intelligence and machine learning · 1 · 1 since 2021Human-computer interaction and ubiquitous computing · 1 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Parallel and multicore computing · 100%
Software engineering, system software, and programming languages
1 paper
Services computing and microservices · 77% Programming languages and type systems · 23%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Services computing and microservices › web service interfaces
RESTful APIs
0.112012
S: a scripting language for high-performance RESTful web services · PPoPP 2012
Parallel and multicore computing
domain-specific language
0.112012
S: a scripting language for high-performance RESTful web services · PPoPP 2012
Parallel and multicore computing
parallel programming models
0.112012
S: a scripting language for high-performance RESTful web services · PPoPP 2012
Programming languages and type systems › domain-specific languages
domain-specific language design
0.012012
S: a scripting language for high-performance RESTful web services · PPoPP 2012

Methods — techniques the papers use, named apart from their topics

explicit and implicit parallelism control · 0.3
YearPublicationVenuePosition
2021 The Virtual Emotion Loop: Towards Emotion-Driven Product Design via Virtual Reality
abstract
Emotions play a significant role in product design for end-users.However, how to take emotions into account is not yet completely understood.We argue that this gap is due to a lack of methodological and technological frameworks for effective investigation of the elicitation conditions related to emotions and corresponding emotional responses of the users.Emotiondriven design should encompass a thorough assessment of users' emotional reactions in relation to certain elicitation conditions.By using Virtual Reality (VR) as mean to perform this investigation, we propose a novel methodological framework, referred to as the VR-Based Emotion-Elicitation-and-Recognition loop (VEE-loop), to close this gap.
Davide Andreoletti, Luca Luceri, Achille Peternier, Tiziano Leidi, Silvia Giordano
FedCSIS3
2014 High-performance execution of service compositions: a multicore-aware engine design
abstract
SUMMARY Although modern computer hardware offers an increasing number of processing elements organized in nonuniform memory access (NUMA) architectures, prevailing middleware engines for executing business processes, workflows, and Web service compositions have not been optimized for properly exploiting the abundant processing resources of such machines. Amongst others, factors limiting performance are inefficient thread scheduling by the operating system, which can result in suboptimal use of system memory and CPU caches, and sequential code sections that cannot take advantage of multiple available cores. In this article, we study the performance of the JOpera process execution engine on recent multicore machines. We first evaluate its performance without any dedicated optimization for multicore hardware, showing that additional cores do not significantly improve performance, although the engine has a multithreaded design. Therefore, we apply optimizations on the basis of replication together with an improved, hardware‐aware usage of the underlying resources such as NUMA nodes and CPU caches. Thanks to our optimizations, we achieve speedups from a factor of 2 up to a factor of 20 (depending on the target machine) when compared with a baseline execution ‘as is’. Copyright © 2012 John Wiley & Sons, Ltd.
Achille Peternier, Cesare Pautasso, Walter Binder, Daniele Bonetta
Concurr. Comput. Pract. Exp.1
2014 Improving execution unit occupancy on SMT-based processors through hardware-aware thread scheduling
Achille Peternier, Danilo Ansaloni, Daniele Bonetta, Cesare Pautasso, Walter Binder
Future Gener. Comput. Syst.1
2013 Parallelism profiling and wall-time prediction for multi-threaded applications
abstract
A detailed and accurate characterization of the parallelism of applications is essential for predicting their wall-time on different platforms, both for an application running in isolation and for a set of consolidated applications executing on the same platform. However, prevailing profilers are often based on sampling and do not provide exact information on the parallelism of the profiled application. In this paper we present a novel profiler that logs all thread scheduling activities within the operating system kernel. These logs enable us to accurately characterize applications' parallelism on a given platform by computing the number of threads that are active at each moment. We also present a simple mathematical prediction model to estimate wall-time for program execution on a k2-core machine using profiles collected using a k1-core machine (of the same architecture and running at the same clock speed). We use our profiler to assess the parallelism of several CPU-bound DaCapo benchmarks and evaluate the accuracy of our prediction model.
Achille Peternier, Walter Binder, Akira Yokokawa, Lydia Y. Chen
ICPE1
2012 Node.Scala: Implicit Parallel Programming for High-Performance Web Services
Daniele Bonetta, Danilo Ansaloni, Achille Peternier, Cesare Pautasso, Walter Binder
Euro-Par3
2012 Hardware-aware Thread Scheduling: The Case of Asymmetric Multicore Processors
abstract
Modern processor architectures are increasingly complex and heterogeneous, often requiring solutions tailored to the specific characteristics of each processor model. In this paper we address this problem by targeting the AMD Bulldozer processor as case study for specific hardware-oriented performance optimizations. The Bulldozer architecture features an asymmetric simultaneous multithreading implementation with shared floating point units (FPUs) and per-core arithmetic logic units (ALUs). Bulld Over, presented in this paper, improves thread scheduling by exploiting this hardware characteristic to increase performance of floating point-intensive workloads on Linux-based operating systems. Bulld Over is a user-space monitoring tool that automatically identifies FPU-intensive threads and schedules them in a more efficient way without requiring any patches or modifications at the kernel level. Our measurements using standard benchmark suites show that speedups of up to 10% can be achieved by simply allowing Bulld Over to monitor applications, without any modification of the workload.
Achille Peternier, Danilo Ansaloni, Daniele Bonetta, Cesare Pautasso, Walter Binder
ICPADS1
2012 S: a scripting language for high-performance RESTful web services
abstract
There is an urgent need for novel programming abstractions to leverage the parallelism in modern multicore machines. We introduce S, a new domain-specific language targeting the server-side scripting of high-performance RESTful Web services. S promotes an innovative programming model based on explicit (control-flow) and implicit (process-level) parallelism control, allowing the service developer to specify which portions of the control-flow should be executed in parallel. For each service, the choice of the best level of parallelism is left to the runtime system. We assess performance and scalability by implementing two non-trivial composite Web services in S. Experiments show that S-based Web services can handle thousands of concurrent client requests on a modern multicore machine.
Daniele Bonetta, Achille Peternier, Cesare Pautasso, Walter Binder
PPoPP2
2011 Towards Self-Organizing Service-Oriented Architectures
abstract
Service-oriented architectures (SOAs) provide a successful model for structuring complex distributed software systems, as they reduce the cost of ownership and ease the creation of new applications by composing existing services. However, currently, the development of service-oriented applications requires many manual tasks and prevailing infrastructure is often based on centralized components that are central points of failure and easily become bottlenecks. In this paper, we promote self-organizing SOA as a new approach to overcome these limitations. Self-organizing SOA integrates research results in the areas of autonomic and service oriented computing. We consider self-organizing features for the whole life-cycle of a service-oriented application, from the creation to the execution, optimization, and monitoring.
Walter Binder, Daniele Bonetta, Cesare Pautasso, Achille Peternier, Diego Milano, Heiko Schuldt, Nenad Stojnic, Boi Faltings, Immanuel Trummer
SERVICES4
2010 A Multicore-Aware Runtime Architecture for Scalable Service Composition
abstract
Middleware for web service orchestration, such as runtime engines for executing business processes, workflows, or web service compositions, can easily become performance bottlenecks when the number of concurrent service requests increases. Many existing process execution engines have been designed to address scalability with distribution and replication techniques. However, the advent of modern multicore machines, comprising several chip multi-processors each offering multiple cores and often featuring a large shared cache, offers the opportunity to redesign the architecture of process execution engines in order to take full advantage of the underlying hardware resources. In this paper we present an innovative process execution engine architecture. Its design takes into account the specific constraints of multicore machines and scales well on different processor architectures, as shown by our extensive performance evaluation. A key feature of the design is self-configuration at startup according to the type and number of available CPUs. We show that our design makes efficient use of the available resources and can scale to run thousands of concurrent business process instances per second, highlighting the potential and the benefits for multicore-awareness in the design of scalable process execution engines.
Daniele Bonetta, Achille Peternier, Cesare Pautasso, Walter Binder
APSCC2
2008 Design and implementation of a wearable, context-aware MR framework for the Chloe@University application
abstract
In this paper, we present the technical details and the challenges we faced during the development and evaluation phases of our wearable indoor guiding system which consists of a virtual personal assistant guiding the user to his/her desired destination. The main issues that will be discussed can be classified in three categories: context detection, real-time 3D rendering and user interaction.
Xavier Righetti, Achille Peternier, Mathieu Hopmann, Daniel Thalmann
ETFA2
2008 A virtual 3D mobile guide in the INTERMEDIA project
Nadia Magnenat-Thalmann, Achille Peternier, Xavier Righetti, Mingyu Lim, George Papagiannakis, Tasos Fragopoulos, Kyriaki Lambropoulou, Paolo Barsocchi, Daniel Thalmann
Vis. Comput.2
2007 Chloe@University: an indoor, mobile mixed reality guidance system
abstract
With the advent of ubiquitous and pervasive computing environments, one of promising applications is a guidance system. In this paper, we propose a mobile mixed reality guide system for indoor environments, [email protected] A mobile computing device (Sony's Ultra Mobile PC) is hidden inside a jacket and a user selects a destination inside a building through voice commands. A 3D virtual assistant then appears in the see-through HMD and guides him/her to destination. Thus, the user simply follows the virtual guide. [email protected] also suggests the most suitable virtual character (e.g. human guide, dog, cat, etc.) based on user preferences and profiles. Depending on user profiles, different security levels and authorizations for content are previewed. Concerning indoor location tracking, WiFi, RFID, and sensor-based methods are integrated in this system to have maximum flexibility. Moreover smart and transparent wireless connectivity provides the user terminal with fast and seamless transition among Access Points (APs). Different AR navigation approaches have been studied: [Olwal 2006], [Elmqvist et al.] and [Newman et al.] work indoors while [Bell et al. 2002] and [Reitmayr and Drummond 2006] are employed outdoors. Accurate tracking and registration is still an open issue and recently it has mostly been tackled by no single method, but mostly through aggregation of tracking and localization methods, mostly based on handheld AR. A truly wearable, HMD based mobile AR navigation aid for both indoors and outdoors with rich 3D content remains an open issue and a very active field of multi-discipline research.
Achille Peternier, Xavier Righetti, Mathieu Hopmann, Daniel Thalmann, Matteo Repetto, George Papagiannakis, Pierre Davy, Mingyu Lim, Nadia Magnenat-Thalmann, Paolo Barsocchi, Tasos Fragopoulos, Dimitrios Serpanos, Yiannis Gialelis, Anna Kirykou
VRST1
2006 Wearable Mixed Reality System In Less Than 1 Pound
Achille Peternier, Frédéric Vexo, Daniel Thalmann
EGVE1