We demonstrate SONOS (silicon-oxide-nitride-oxide-silicon) analog memory arrays that are optimized for neural network inference. The devices are fabricated in a 40nm process and operated in the subthreshold regime for in-memory matrix multiplication. Subthreshold operation enables low conductances to be implemented with low error, which matches the typical weight distribution of neural networks, which is heavily skewed toward near-zero values. This leads to high accuracy in the presence of programming errors and process variations. We simulate the end-to-end neural network inference accuracy, accounting for the measured programming error, read noise, and retention loss in a fabricated SONOS array. Evaluated on the ImageNet dataset using ResNet50, the accuracy using a SONOS system is within 2.16% of floating-point accuracy without any retraining. The unique error properties and high On/Off ratio of the SONOS device allow scaling to large arrays without bit slicing, and enable an inference architecture that achieves 20 TOPS/W on ResNet50, a$> 10\times $gain in energy efficiency over state-of-the-art digital and analog inference accelerators.

Design rule check (DRC) violations after detailed routing prevent a design from being taped out. To solve this problem, state-of-the-art commercial EDA tools global-route the design to produce a global-route congestion map; this map is used by the placer to optimize the placement of the design to reduce detailed-route DRC violations. However, in sub-14nm processes and beyond, DRCs arising from multiple patterning and pin-access constraints drastically weaken the correlation between global-route congestion and detailed-route DRC violations. Hence, the placer|based on the global-route congestion map|may leave too many detailed-route DRC violations to be fixed manually by designers. In this paper, we present a method that employs (1) machine-learning techniques to effectively predict detailed-route DRC violations after global routing and (2) detailed placement techniques to effectively reduce detailed-route DRC violations. We demonstrate on several layouts of a sub-14nm industrial design that this method predicts the locations of 74% of the detailed-route DRCs (with false positive prediction rate below 0.2%) and automatically reduces the number of detailed-route DRC violations by up to 5x. Whereas previous works on machine learning for routability [30] [4] have focused on routability prediction at the floorplanning and placement stages, ours is the first paper that not only predicts the actual locations of detailed-route DRC violations but furthermore optimizes the design to significantly reduce such violations.

Storage-class memory technologies such as phase-change memory and memristors present a radically different interface to storage than existing block devices. As a result, they provide a unique opportunity to re-examine storage architectures. We find that the existing kernel-based stack of components, well suited for disks, unnecessarily limits the design and implementation of file systems for this new technology.

In this paper, we present a tribute to Professor C. L. (David) Liu for his numerous contributions in the field of the physical design of VLSI circuits by highlighting some of his work in the area of routing in general, and performance-driven routing in particular. We point out how he pioneered several important problem formulations along with elegant algorithmic solutions for them, often 5-10 years ahead of the time when they would become important in the semiconductor industry. More specifically, we present a brief discussion of his work on the problems of interconnect crosstalk optimization and performance-driven layer assignment, showing how it influenced subsequent academic research as well as the evolution of industrial layout tools, as an illustration of his visionary and transformative approach to physical design.

The six selected papers exemplify the broad scope of modern physical design (PD), covering system-level physical synthesis, layout optimization, analog circuit placement, beyond-die routing, biochip design automation, and emerging device performance optimization.

The five regular papers and three short papers in this special section were carefully selected from the 2009 Association for Computing Machinery International Symposium on Physical Design (ISPD) Technical Program.

In modern designs, the delay of a net can vary significantly depending on its routing. This large estimation error during the pre-routing stage can often mislead the optimization of the netlist. We extend state-of-the-art interconnect-driven physical synthesis by introducing a new paradigm (namely, persistence) that relies on guaranteed net routes for the most sensitive nets while performing circuit optimization in the pre-route stage. We implemented our proposed approach in a cutting-edge industrial physical synthesis flow; this involved the automatic identification and routing of critical nets that were likely to be mispredicted, the automatic update of their routes during the subsequent pre-routing stage optimizations, and the guaranteed retention of their routes across the routing stage. Our approach achieves significant performance improvements on a suite of real-world 65nm designs, while ensuring that the impact on their routability remains negligible. Furthermore, our experimental results scale very well with design size.

Recent studies have shown that scaling causes the number of repeaters to grow rapidly. The author demonstrates that this growth leads to massive placement perturbations that break the convergence of today's interleaved placement and repeater-insertion flows. The author then presents two new force models for repeaters targeted towards quadratic placement algorithms. Finally, experiments demonstrate the effectiveness of the repeater modeling technique in preserving placement convergence (often accompanied by wire-length improvement) at the 45- and 32-nm technology nodes

Routing congestion has become a serious concern in today's very-large-scale-integration designs. To address this, the authors propose a technology mapping algorithm that minimizes routing congestion under delay constraints in this paper. The algorithm employs a dynamic-programming framework in the matching phase to generate probabilistic congestion maps for all the matches. These congestion maps are then utilized to minimize routing congestion during the covering, which preserves the delay optimality of the solution using the notion of slack. Experimental results on benchmark circuits in a 100-nm technology show that the algorithm can improve track overflows significantly as compared to conventional technology mapping while satisfying delay constraints.

We present a practical flow that automates the process of analyzing noise failures and determining and implementing the most appropriate design fixes in high performance designs. For each noise problem, the flow implicitly identifies the most sensitive relevant electrical parameter(s) which it then maps to a physical solution that minimizes design perturbation. Integrated with standard physical synthesis, it was used extensively in a high volume 90 nm multi-GHz microprocessor project.

We demonstrate how to use placement to ameliorate the predicted repeater explosion problem caused by poor interconnect scaling. We achieve repeater count reduction by dynamically modifying net weights in a context-sensitive manner during global placement and coarse legalization. Our scheme, which models layer assignment as well as valid inter-repeater distance ranges, can decrease the repeater counts significantly with minimal impact on wirelength.

Routing congestion has become a serious concern in today's VLSI designs. In this paper, we propose a technology mapping algorithm that minimizes routing congestion under delay constraints. The algorithm employs a dynamic programming framework in the matching phase to generate probabilistic congestion maps for all the matches. These congestion maps are then utilized to minimize routing congestion during the covering, which preserves the delay-optimality of the solution using the notion of slack. Experimental results on benchmark circuits in a 100 nm technology show that the algorithm can improve track overflows by 44%, on an average, as compared to the conventional technology mapping while satisfying delay constraints.

Due to increasing design complexities, routing congestion has become a critical problem in very large scale integration designs. This paper introduces a distributed metric to predict routing congestion and applies it to technology mapping that targets area and delay optimization. Our technology mapping algorithms are guided by a probabilistic congestion map for the subject graph to identify the congested regions, where congestion-optimal matches are favored. Experimental results on a set of benchmark circuits in a 90-nm technology show that congestion-aware mapping results in a reduction of 37%, on an average, in track overflows with marginal gate-area penalty as compared to conventional area-oriented technology mapping. For delay-oriented mapping, our algorithm improves track overflows by 20%, on an average, in addition to preserving or improving the delay, as compared to the conventional method.

Recent works have shown that scaling causes the number of repeaters to grow rapidly. We demonstrate that this growth leads to massive placement perturbations that break the convergence of today's interleaved placement and repeater insertion flows. We then present two new force models for repeaters targeted towards analytical placement algorithms. Our experiments demonstrate the effectiveness of our repeater modeling technique in preserving placement convergence (often also accompanied by wire-length improvement) at the 45 and 32 nm technology nodes.

One of the often-overlooked aspects of Moore's law is that it is predicated solely on device performance scaling linearly with dimension. Yet scaled interconnect performance has remained essentially constant. The physics of the problem is rather brutal; while capacitance drops with the reduced length of interconnect, its resistance rises and the RC time product is constant under uniform scaling, greatly lagging scaled device performance. In the late-eighties, one micron process dimensions had little wire resistance and the RC delay component of interconnect was negligible. But as process dimensions scaled below one-quarter micron in the late nineties, fears of interconnect delay dominance reached a fevered pitch in the physical design community. Speculation ran rampant that resistive interconnects would soon dominate the performance of design. We dub this era the Rise of the Interconnect Chicken Little.In 1998, Keutzer and Sylvester sought to dispel the hype associated with these wire-related problems, arguing that appropriate device sizing and use of design hierarchy would prevent significant exposure to RC delay in synthesis blocks of 50K gates or less. Their argument was supported by the then-prevalent wisdom that interconnect delay was not dominant and that sharp designers and process engineers could work their way around this problem. We'll dub this general consensus as the Interconnect Ostrich point of view. The following year, Ho and Horowitz attempted to reinvigorate the Chicken Little argument in a publication challenging the Keutzer/Sylvester viewpoint with yet more data on interconnect scaling, but this interconnect-debate-through-papers yielded little change-of-heart on either side. Many other deep-submicron issues have since captured the attention of the designer (e.g., coupling noise, IR drop, and MOSFET leakage) and the interconnect paper-debate generally faded to the background.Recently, however, projections of historical scaling trends by Saxena, et al, have predicted synthesis blocks with 70% (!) of their cell count dedicated to interconnect buffers within a few process generations, raising both skepticism and fearful reactions in the physical design community. While we might think of this as the Return of Chicken Little, the debate has grown far more complex: competition over wiring resources with power supply and clock, concern over noise, and the potential for degraded device performance due to leakage all cast their shadow over this issue. Some now argue we need to consider more exotic circuitry or even restrict our VLSI architectures dramatically. Rather than wait for this debate to rage on in future physical design publications, the time is now to have the Great Interconnect Debate, the subject of this panel.

Due to increasing design complexity, routing congestion has become a critical problem in VLSI designs. This paper introduces a distributed metric to predict routing congestion for a premapped netlist and applies it to technology mapping that targets area optimization. Our technology mapping algorithm is guided by a probabilistic congestion map for the subject graph to identify the congested regions. Experimental results on the benchmark circuits in a 90nm technology show that congestion-aware mapping results in a reduction of 37%, on an average, in track overflows as compared to conventional technology mapping.

We study scaling in the context of typical block-level wiring distributions, and identify its impact on the design process. In particular, we study the implications of exponentially increasing repeater and clocked repeater counts on the algorithms and methodologies used for physical synthesis and full-chip assembly, showing that mere capacity scaling of current algorithms and methodologies is insufficient to handle the new challenges. Finally, we suggest a few approaches to tackle these challenges by constructing a case for abstract fabrics.

We present the results of scaling studies in the context of typical block-level wiring distributions, and study the impact of the identified trends on the post-RTL design process. In particular, we look at the implications of exponentially increasing repeater and clocked repeater counts on the algorithms and methodologies used for logic synthesis, technology mapping, layout, and full-chip assembly, and identify several new research problems relevant to future designs. Next, we introduce the basic principles of correct-by-construction (CbC) design. We look at some techniques for post-RTL design meeting CbC philosophy, and then construct a case for flexible, abstract fabrics. Finally, we suggest CbC approaches to tackle the new synthesis and layout challenges identified in this paper.

With worsening crosstalk in nanometer designs, it is increasingly important to control the switching cross-coupling experienced by critical wires. This is commonly done by inserting shields adjacent to these wires. However, the number of shielded wires can become extremely large, resulting in a large area impact. We address this problem at both the methodological and algorithmic levels, integrating the traditionally separate steps of power and signal routing in a safe manner to minimize the number of shields required to satisfy all shielding constraints. We propose a new abstraction for the block-level global and detailed routing hierarchy that allows accurate early estimation of crosstalk. Furthermore, we postpone the power routing in middle metal layers to after critical signal nets and their shields have been laid out (with maximal shield sharing), and then try to construct a fine-grained power grid out of the already routed shields. Given a routing on a metal layer, our adaptive power routing algorithm adds provably fewest new power lines to complete the power grid on that layer while guaranteeing adequate power delivery. Our approach has proven effective while designing some high-frequency blocks of a commercial gigahertz range microprocessor using a 0.18-/spl mu/m process technology.

Coupling effect due to line-to-line capacitance is of serious concern in timing analysis of circuits in ultra deep submicrometer CMOS technology. Often coupling delay is heavily dependent on temporal correlation of signal switching in relevant wires. Temporal decorrelation by shifting timing window can alleviate performance degradation induced by tight coupling. This paper presents an algorithm for minimizing circuit delay through timing window modulation in dual V/sub t/ technology. Experimental results on the ISCAS85 benchmark circuits indicate that the critical delay will be reduced significantly when low V/sub t/ is applied properly.

System structure and a taped out 0.18u 2 GHz product application result are described for a domino synthesis capability that covers all aspects of domino design, from estimation to silicon-ready layout, with custom-class optimization. The described optimization flow, abstraction modes, and key cost factors deliver power-optimized, noise-correct domino performance on complex logic.

With worsening crosstalk in nanometer designs, it is becoming increasingly important to control the switching cross-coupling experienced by critical wires. This is commonly done by adding shields adjacent to these wires. However, the number of wires requiring shields in high frequency designs becomes extremely large, resulting in a large area impact. We address this problem at both the methodological and algorithmic levels in this paper, integrating the traditionally separate steps of power and signal routing in a safe manner to minimize the number of shields required to satisfy all shielding constraints. We postpone the power routing in middle metal layers to after critical signal nets and their shields have been laid out (with maximal shield sharing), and then try to construct a fine-grained power grid out of the already routed shields. Given a routing on a metal layer, our adaptive power routing algorithm adds provably fewest new power lines to complete the power grid on that layer. Our approach has proven highly effective while designing some high frequency blocks of a commercial gigahertz range microprocessor.

Coupling effect due to line-to-line capacitance is of serious concern in timing analysis of circuits in ultra deep submicron CMOS technology. Often coupling delay is strongly dependent on temporal correlation of signal switching in relevant wires. Temporal decorrelation by shifting timing window can alleviate performance degradation induced by tight coupling. This paper presents an algorithm for minimizing circuit delay through timing window modulation in dual $V_t$ technology. Experimental results on the ISCAS85 benchmark circuits indicate that the critical delay will be reduced significantly when low $V_t$ is applied properly.

Traditionally, interconnects in multilayer routing technologies have been routed greedily, one at a time. This yields good routings for the first few interconnect trees, but poor routings for the remaining trees. In contrast, we present a new performance-driven approach for layer assignment and routing in which the quality of the routing is largely order independent, minimizing the peak tree delays in the process. We introduce a dynamically adjusted area quota for each tree on each routing layer. This ensures that no tree uses up excessive routing space on the "good" layers. Since the parasitic coupling of different layers varies over a large range, assignment of the edges in the trees to specific routing layers has a large impact on the interconnect delay. Furthermore, we derive an expression for the contribution of an edge in a tree to the total delay of that tree as a function of the layer to which the edge is assigned. We use this expression to introduce a lookahead key for each edge of each tree that enables us to decide whether to route that edge immediately on the current layer or to postpone it to a subsequent layer. Our approach can be used to construct a performance-driven layer assignment and routing algorithm specifically tailored toward any given combination of the timing, routing and technology models. Our experimental results demonstrate that this approach consistently outperforms the multipass greedy scheme currently in vogue, both in worst case delay and in routability.

Much of the previous work on crosstalk minimization attempted to handle crosstalk during the process of routing the nets. However, this necessitates the estimation of the expected crosstalk due to nets that are yet to be routed. In contrast, post-processing algorithms can use accurate crosstalk measurements to respace the wires, thus improving the crosstalk even in routings produced by crosstalk-aware routers. However, the postprocessing algorithms presented so far have been restricted either by the use of a gridded model or by the difficulty of optimizing the highly nonlinear crosstalk-based objective functions. We address the problem of minimizing the peak crosstalk in a routed region by respacing its critical nets and their neighbors. We study the variation of the crosstalk in a net and its neighbors when one of its trunks is perturbed, showing that the trunk's perturbation range can be efficiently divided into subintervals having monotonic or unimodal crosstalk variation. This result enables us to determine the optimum location for the trunk without needing to solve any nonlinear equations. Using this, we construct an algorithm to minimize the peak crosstalk in the nets of a gridless channel. Although we present our results in terms of channel routing, our theory is also applicable to more general routing models. Furthermore, our crosstalk model subsumes the models used in most prior works on noise-aware routing. Our experiments verify the effectiveness of our approach.

We study the variation of the crosstalk in a net and its neighbors when one of its trunks is perturbed, showing that the trunk's perturbation range can be efficiently divided into subintervals having monotonic or unimodal crosstalk variation.We can therefore determine the optimum trunk location without solving any non-linear equations.Using this, we construct and experimentally verify an algorithm to minimize the peak net crosstalk in a gridless channel.

With the advent of DSM technologies, interconnect delays increasingly overshadow the transistor delays. Furthermore, since the electrical characteristics of di#erentlayers in multilayer routing technologies vary widely, the assignment of the interconnect tree edges to speci#c routing layers has a large impact on the interconnect delays. Traditionally, critical global interconnect trees were routed greedily, one at a time. This caused the #good" layers to be used up largely for the #rst few trees, yielding poor routings for the remaining trees. Multiple passes with di#erent tree orderings were usually used to remedy the situation, although with limited success. We propose the use of dynamically adjusted area quotas to prevent the #rst few trees from monopolizing the #good" layers. Our approach is independent of the routing model or the router employed, and reduces the maximum tree delays by around 15# as compared to traditional algorithms. 1 Introduction The traditional problem of ass...