Design of a multithreaded, object oriented C++ class library for a simple LAN/WAN gateway application is described. The design supports both the algorithm used in various existing commercial products and another simple and enhanced algorithm. The design takes advantage of the inheritance and polymorphism properties of the object oriented paradigm, is based on Remote Procedure Calls (RPCs), and is expressed in terms of a portable, heterogeneous set of port objects. The multithreaded performance is modelled, and is compared to long duration observed values. RPC environments are becoming widespread, but their application-level performance characteristics are not well-understood. This experiment is one of the first such reported for object-oriented RPC environments. Instructive observations, based on this experience, about the library and concurrent RPC performance modelling technique are presented.

Abstract A predominant (‘base’) scheme currently used in many circuit‐switched LAN‐WAN gateway applications is based on device‐driver LAN redirections. Various functional and performance deficiencies associated with the LAN redirection (base) scheme and an RPC programming interface are described. This RPC definition supports the base scheme, as well as another (‘enhanced’) scheme. The enhanced scheme overcomes the various outlined functional deficiencies associated with the cited implementations of the base scheme. Implementations of these two client‐server application schemes on top of the IEEE portable operating‐system interface and the Open Software Foundation RPC are described for both schemes. Performances of these two schemes are compared, both based on a simplified Markov chain model and on actual implementations and long‐duration experiments. Some of the similarities between the predictive simple‐model behaviors and the actual experienced results for the applications are encouraging. This experience shows that the described RPC programming interface is a reasonable candidate for immediate practical implementations on heterogeneous systems.

A novel implementation of a Two-dimensional FFT array processor is given. The reasons for its superior performance is the one-to-one and onto mapping of the problem communications topology onto the interconnection network, VLSI-based implementation, a proper choice for the number system, multiple-parallelism, and the use of packet-switching as opposed to circuit switching. A performance comparison also presented.