This paper presents a power quality evaluation of the Class-D high-frequency power amplifier/inverter. The real, reactive, complex, apparent, distortion, and non-active powers at the input of the resonant circuit are derived and illustrated as functions of frequency. Also, the total harmonic distortion and power factor are determined. Similar analysis of the power quality at the dc input of the amplifier is given. Experimental results are given to verify the theory. It is shown that the input current of the Class-D inverter contains a significant ac component that does not contribute to the real dc input power, resulting in high distortion power, high total harmonic distortion, and poor power factor. The Class-D inverter was designed, built and tested to verify the theory.

This paper presents an analysis of an LCR second-order low-pass filter capacitor to achieve a specified ripple output voltage in Buck, forward, Zeta, and Ćuk PWM DC-DC power converters for continuous-conduction mode (CCM). Current and voltage waveforms across output filter components are derived. Using the waveform of the ac component of the output voltage, an expression for the ripple voltage is developed in terms of the filter capacitance and equivalent series resistance. The results can be used for all PWM converters with the LCR output filter, such as Buck, forward, Zeta, and Ćuk PWM DC-DC converters. Theoretical results were in good agreement with simulation and experimental results.

In this paper, an averaged nonlinear model of a bridgeless single-switch non-inverting ac-dc Cuk converter in DCM is derived. In addition, a current-mode control scheme is designed to operate the power converter in buck and boost modes during line and load variations. In contrast, the previous research endeavors of the bridgeless Cuk converter presented a single operation mode, and accommodation of large disturbances has not been discussed. The proposed control method is compared with the classical PI controller to investigate their performance. MATLAB simulation results show that the proposed control scheme improves the dynamical response, tracks the reference voltage, and provides wide operating range.

A Wireless Power Transfer System (WPTS) is basically constituted by two main parts: the primary side and the secondary side. Beyond the application related with the power transfer, also data communication between these two sides can be implemented and it can have a fundamental importance. In this paper, a classification that highlights the advantages and the disadvantages of different data communication techniques available in the literature is shown. The single link dual carrier (SLDC) technique is studied in depth, analysing transfer function of the power and data transmitting channels. A design example for electric vehicle wireless charging application in a Series-Series (SS) compensated system is presented. The analytical models are validated through simulations.

This paper presents a novel means of controlling a dynamic power supply in continuous conduction mode via sliding-mode voltage control technique. Previous work has discussed the design and implementation of a high-efficiency dynamic power supply based on an asynchronous buck converter in open-loop operation. This work incorporates nonlinear control design for the dynamic buck converter that suits applications such as envelope tracking and amplitude modulation for Class E power amplifiers. The control system is shown, via MATLAB simulation, to accurately track time-varying reference signals, improve the power converter dynamics, and provide the desired output power while rejecting large load disturbances.

LLC resonant converters offer high efficiency at high frequencies because of their ability to achieve Zero Voltage Switching (ZVS) or Zero Current Switching (ZCS). However, they require a variable frequency control, which generates a wide range of harmonics and causes electromagnetic compatibility issues. The frequency control reduces the converter efficiency at lighter loads and fails to maintain monotonicity of the control power to output transfer function. These limitations are dramatically improved by phase shift modulation (PSM) technique, which is studied in this paper. PSM controlled technique in full-bridge converter, not only improve the monotonicity of the power supply control to output transfer function, but also improves the power supply efficiency at light loads. A systematic analysis and characteristics of a PSM LLC resonant converter is proposed in this paper along with a comparison with conventional frequency modulated (FM) controlled LLC converter. The simulated PSM controlled LLC topology exhibited a maximum peak efficiency of 97.47%. At lighter load conditions, it records an efficiency of 91.66% while the FM controlled converter recorded only 82.8 %. In addition, PSM has a better control of leakage, magnetizing, and resonant currents, which results in a superior behavior than conventional FM converters.

In this paper, a nonlinear approach to modeling DC-DC PWM converters in continuous conduction mode (CCM) is presented. Specifically, a converter nonlinear model is implemented in MATLAB and SIMULINK for both the case without parasitic components (ideal case) and with parasitic components (non-ideal case). The implementation, which is based on the analytical computation of the periodic solutions in the high frequency steady-state operating condition, makes it possible to perform a systematic analysis of the dynamical behavior induced by the various perturbation sources acting on the converters. A comparison of the dynamics generated in the ideal and nonideal cases by step changes in duty cycle, input voltage and load resistance is reported for both the boost and buck converters.

DC-DC pulse-width modulated (PWM) converters are nonlinear systems that require control circuits to obtain the desired output voltage. These control circuits are often designed using linearized models of the converters, so modeling is a relevant topic for the design of performing closed-loop converters. In this paper, the nonlinear nature of DC-DC PWM converters operated under continuous conduction mode (CCM) is considered. It is first shown how the exact periodic solutions can be analytically computed for the nonlinear converter model in the high-frequency steady-state operating condition. Also, a nonlinear variation model, which characterizes the closed-loop dynamics, induced by perturbations of the steady state, is provided. The nonlinear models and the analytical periodic solutions are implemented in MATLAB and SIMULINK and applied to a boost converter subject to parasitic components. In particular, the behavior to step changes in duty cycle, input voltage, and load resistance are compared with the results obtained using small-signal circuit averaging techniques.

In this paper, a nonlinear model of inverting pulse-width-modulated buck-boost converter for continuous conduction mode is introduced based on the large-signal averaging technique. The simulation of the nonlinear buck-boost model is performed in MATLAB/SIMULINK and compared with the corresponding circuit in SaberRD simulator for validation purpose. Additionally, a nonlinear control scheme of cascaded proportional-integral sliding-mode current controller is designed. The equivalent control law, existence, and stability conditions are introduced. The simulation results show that the proposed control system enhances the regulation performance, removes the steady-state error, and provides robust tracking against large disturbances.

This paper introduces a new switched-mode ZVS inverter that is suited to operate at high frequencies with rapid transitions. This topology includes small passive storage elements, low-voltage stress, and fast dynamic response. The single-switch inverter, which has a ground-ended transistor, can be implemented to achieve zero-voltage switching at switching frequencies of several MHz. A tuned resonant network is utilized to alleviate switch voltage stress. The resonant network, which has the desired drain-source impedance, shapes the switch voltage into a quasi-rectangular waveform. The principle of operation, design procedure, and power loss analysis of the proposed circuit are given. The new circuit prototype is designed, simulated, and built at 20 MHz. The performance of the topology is also demonstrated via experimental results. The proposed circuit can be used as a gate-drive circuit for high frequency applications.

This paper presents a completely new technique developed to locate a single parametric fault in DC-DC power converters by means of time-domain measurements or simulations, following a rigorous approach. The technique is composed by three separated stages, a first one which evaluates testability and ambiguity groups of the Converter (or, more in general, the Circuit) Under Test (CUT), a second one which localizes the fault, classifying it in an appropriate Fault Class (FC) and a last one (optional) that can extract the value of the faulty component. The fabrication tolerances of the healthy components are taken into account at each stage of the method.

The PWM DC-DC boost converters are nonlinear time-variant circuits that provide a constant output voltage higher than input voltage over a wide duty-cycle range. In this paper, a large-signal non-ideal averaged model of boost converter is implemented using MATLAB s-function. In addition, voltage-mode control with type III compensator is designed to improve the system response and relative stability. The nonlinear model is validated via MATLAB and SaberRD simulations. Finally, the proposed model is used to study the tracking performance and stability of the control system under line and load disturbances.

This paper proposes a new single-switch gate-driver circuit to drive a low-side power transistor at high frequencies with rapid turn-ON and turn-OFF transitions. The characteristics of the proposed topology include fast dynamic response, small energy storage requirements, and flexible design. Conventional gate drivers are used up to frequencies around 5 MHz and need at least two transistors. In this study, detailed description, design procedure, and power loss analysis of the proposed topology are presented. The introduced circuit exhibits fast switching speed and low gate-drive loss. Simulation and experimental results showing performance of the new topology are provided to validate the theory. The prototype of the gate driver for power transistors is designed, simulated, and tested at 20 MHz.

This paper presents a small-signal analysis of the power stage of a tapped-inductor pulse-width modulated (PWM) buck dc-dc converter, operating in continuous-conduction mode (CCM). Using the circuit averaging technique, the small-signal model of the power stage is developed. The derivation of duty cycle-to-output voltage and input-to-output voltage transfer functions are presented. An example tapped inductor buck dc-dc converter is considered. The time-domain and frequency-domain characteristics of the converter are analyzed, illustrated, and discussed. The theoretical results are validated using circuit simulations.

This paper presents the following for a full-bridge Class-DE resonant inverter operating at a fixed duty ratio: (a) steady-state analysis using first-harmonic approximation and (b) derivation of closed-form expressions for the currents, voltages, and powers. The conversion from a series-parallel resonant network to a series resonant network is presented. Imposing the zero-voltage and zero-derivative switching conditions, the expression for a shunt capacitance across the MOSFETs in the inverter bridge is derived. The closed-form expressions to calculate the values of the resonant components are presented. A practical design of a Class-DE resonant inverter supplied by a dc input voltage of 230 V, delivering an output power of 920 W, and operating at a switching frequency of 100 kHz is considered and its design methodology is included. Theoretical results are validated by Saber simulations.

This paper presents the small-signal modeling of a dual-SEPIC dc-dc converter power stage operating in continuous-conduction mode using the circuit averaging technique. The converter component parasitic resistances are taken into account. From the small-signal model, the following expressions of the converter required to design the outer voltage loop are derived: duty cycle-to-output voltage and input-to-output voltage transfer functions, input impedance, and output impedance. A design example is given and the characteristics of these transfer functions are analyzed. Simulations are performed to verify the correctness of the theoretically obtained transfer functions. The dual-SEPIC converter has four reactive components and yields transfer functions of order two. A brief discussion on this aspect is also provided.

This paper presents the following for a Class-E zero-voltage switching (ZVS) power amplifier: (a) design of the choke inductor and (b) theoretical estimation of power losses in the core and a solid round winding. The expressions required to design the core using the Area-Product (Ap) method are provided. The equations for the dc resistance, ac resistance at high frequencies, and dc and ac power losses are provided for the solid round winding. A Class-E ZVS power amplifier with practical specifications is considered. A core with air gap is selected since the choke inductor carries a dc current in addition to the ac component. The gapped core power loss density and power loss are estimated using Steinmetz empirical equation. Simulation results showing the transient analysis and Fourier analysis are given. It is shown that, for the given design, the winding power loss due to the fundamental component is dominant and that due to higher order harmonics can be neglected. In addition, it is also proven that the power loss caused by the dc current component is higher than that by the ac current component, which can be neglected.

The design of Class-E zero-voltage switching (ZVS) inverter with a loosely-coupled transformer is introduced in this paper. In the presented approach, the magnetizing and leakage inductances of the transformer are absorbed into the main circuit. The synthesis of the transformer-version of Class-E ZVS inverter into its equivalent π2a topology is presented. The π2a topology improves the range of the optimum load resistance required to achieve ZVS. An example of the Class-E inverter with dc supply voltage 10 V, output power 10 W, switching frequency 100 kHz and at a coupling coefficient of 0.77 is considered. The inverter is designed to achieve both zero-voltage switching (ZVS) and zero derivative switching (ZDS) conditions. The analytical expressions are validated through simulation results for an optimum coupling coefficient of 0.77. In view of potential misalignment between the primary and secondary coils, simulation results are provided for coupling coefficients, which are lower and higher than the optimum value. It is shown that both ZVS and ZDS can be achieved at a coupling coefficient lower than the optimum value and is not possible to achieve ZVS at a coupling coefficient higher than the optimum value. Overall efficiency of 94.3% is achieved at a coupling coefficient of 0.77, 93.4% at 0.85, and 92.12% at 0.7. The presented approach can be used for transformers with reactive load impedances also.

This paper proposes a technique to track and regulate the “true average” current in any branch of a pulse-width modulated dc-dc power converter. An example buck converter in continuous-conduction mode is considered. A comprehensive characterization is presented for the proposed scheme. An overall dc and small-signal analysis of the inner current loop is performed. The current average current-mode control methods suffer from switching instability at low duty ratios due to a large ripple in the sensed current. Moreover, the current error amplifier's high-frequency pole located at the switching frequency neither alleviates the stability issue nor improves the dynamic response of the converter. In the proposed approach, a low-pass filter, which attenuates any high-frequency ripple is placed in the feedback path of the current loop. Consequently, the control voltage is nearly dc and proportional to the actual average value of the inductor current. The inner current loop gain transfer function of the presented circuit has been derived. The following critical path closed-loop transfer functions have been derived: reference voltage-to-inductor current and reference voltage-to-output voltage. Using practical specifications of a buck dc-dc converter, a theoretical framework to design the inner loop is presented. Verification of the theoretically predicted transfer functions and transient analysis is performed through simulations.

This paper presents a design procedure for wireless power transfer (WPT) systems based on the class-E2 dc-dc converter, taking into account inductive coupling-coil optimizations. The WPT system model is formulated as an equivalent circuit model by expressing the inductive coupled part as a transformer with low-coupling coefficient and equivalent resistances of primary and secondary coils. By using the circuit model, the dc-to-dc efficiency can be obtained analytically. The dc-to-dc efficiency, which is a cost function for optimization, is expressed as functions of physical parameters, such as coil size, wire type, and number of turns. The particle swarm optimization (PSO) is applied for reduction of the computational complexity compared with previous design method [1] and maximization of the cost function in this paper. Experimental results showed the validity and the usefulness of the proposed design procedure.

The following closed-loop transfer functions of the boost converter operating in continuous-conduction mode (CCM) supplying a complex impedance load are derived and analyzed: input-to-output voltage Mvcland reference-to-output Tcl. The load of the boost dc-dc converter is composed of a series-connected resistance and inductance. The dynamic characteristics of the closed-loop boost converter with a third-order double-lead integral compensator are evaluated for different load inductances. The theoretically predicted results are validated through switching-circuit simulations using a suitable converter design example.

This paper presents the analysis and design of the pulse-width modulated (PWM) buck dc-ac converter used as a dynamic power supply for amplitude-modulated class-E radio-frequency (RF) power amplifier (PA). The buck dc-ac converter operates at a fixed input voltage and a variable output voltage. The differences in the inductor current profiles of the buck dc-ac converter and the classical buck dc-dc converter are highlighted. The design equations required to estimate the minimum value of the inductance of the buck dc-ac converter in continuous-conduction mode and consequently, the minimum value of capacitance are derived. A suitable design example is presented for the buck dc-ac converter operating at a fixed input voltage VI = 14 V, a variable output voltage 2 V ≤ VDD ≤ 12 V, switching frequency fs = 100 kHz and supplying power to a class-E RFPA with a maximum output power PO = 10 W and a carrier frequency fc = 1 MHz. Simulations are performed for the buck dc-ac converter and class-E RFPA comprising of gallium-nitride (GaN) field-effect transistors. In this paper, the anti-parallel diode of the GaN transistor is used as the freewheeling diode in the buck converter. Finally, few concluding remarks discussing the effectiveness of the buck converter as an amplitude-modulator is presented.

This paper presents a small-signal analysis of the pulse-width modulated (PWM) boost dc-dc converters operating in continuous-conduction mode (CCM) and subject to complex impedance load. Using the existing knowledge on the small-signal model of the boost converter obtained through the circuit averaging approach, this paper presents an extended analysis of the small-signal transfer functions, under the influence of resistive and inductive load impedances. The expressions for the control-to-output, input-to-output voltage transfer functions, and the output impedance of the boost converter operating in CCM are derived. The characteristics of these transfer functions are analyzed and the effect of the added inductance on the location of poles and zeros is discussed. It is shown that the inherent right-half plane (RHP) zero shifts to the left-half of the s-plane, when the load inductance is increased beyond a specific value. The theoretical results are validated by simulations of a boost converter with suitable design specifications.

This paper presents the derivation of the small-signal model of the boost converter operating in the boundary-conduction mode (BCM) using the circuit averaging technique. The essential transfer functions such as the input-to-output voltage transfer function Mvand the control-to-output transfer function Tpare derived using the linear small-signal model. Further, the characteristics of these transfer functions are analyzed using a representative design example. The switching circuit and the small-signal model are tested on a simulator to validate the proposed model.

The quadratic buck converter or the BUCK converter presents a non-linear dc-dc voltage conversion ratio. The large-signal model of the quadratic buck converter would possess greater number of higher order nonlinear ac terms compared to that of the conventional buck converter. One can gain better insight by considering the linear model to understand the dynamic characteristics of these converters. This paper presents the small-signal model of the open-loop lossy quadratic buck converter operating in continuous conduction mode (CCM). The dc, averaged, and the low-frequency linear equivalent models are developed using the circuit averaging technique. The small-signal transfer functions such as: control-to-output voltage transfer function (Tp), input-to-output voltage transfer function (Mv), input impedance (Zi), and the output impedance (Zo) are derived. A quadratic buck converter with an input voltage of 24 V and an output voltage of 10 V at an output power of 10 W is considered and its equivalent circuit is simulated. The simulation results are provided in order to validate the presented small-signal model.

Different control loops employed in regulating deck converter outputs may have an effect on the output impedance of the converter. In this manuscript, the effect of the inner-current loop on the output impedance of a peak current-mode controlled PWM dc-dc converter with the outer-voltage loop open is investigated. Closed-loop output impedance including feed-forward gains with inner-current loop closed and outer-voltage loop open for peak-current mode controlled PWM dc-dc converters operating in CCM is derived. Bode plots of the closed-loop output impedance for PCM controlled PWM dc-dc buck and boost converters with inner-current loop only are illustrated using MATLAB simulations and are compared with the Bode plots of respective open-loop output impedances.

A new family of Class D resonant inverters is proposed in this paper. Multiple identical series resonant inverters are paralleled using intercell transformers to form phase-controlled multiphase resonant inverter with a common resonant circuit. Inverters can operate at constant frequency utilizing phase-shift control to regulate output. A frequency-domain analysis of the proposed family is performed. An experimental prototype of a three-phase resonant inverter with common resonant circuit was built and extensively tested at an output power of 550 W and switching frequency of 167 kHz.

This paper presents a resonant inductive coupling wireless power transfer (RIC-WPT) system with a class-E2dc-dc converter along with its analytical design procedure. By using the class-E inverter as a transmitter and the class-E rectifier as a receiver, the designed WPT system can achieve a high power-conversion efficiency because of the class-E ZVS/ZDS conditions satisfied in both the inverter and the rectifier. In the simulation results, the system achieved 65.9 % overall efficiency at 5 W (50 Ω) output power, coil distance 30 cm, and 5 MHz operating frequency. Additionally, the simulation results showed good agreement with the design specifications, which indicates the validity of the design procedure.

A unified model including feed-forward gains to derive the control-to-output transfer function of peak current-mode controlled PWM dc-dc converters for CCM is presented. The control-to-output transfer functions for peak current-mode controlled PWM dc-dc buck-boost, boost, and buck converters are derived and illustrated for selected values of perturbation ratio using MATLAB. The proposed model is experimentally verified for peak current-mode controlled buck converter operating in CCM.

A complete block diagram including feedforward gains to derive the audio-susceptibility for the inner-current loop of peak current-mode controlled PWM dc-dc converter operating in continuous conduction mode is proposed. Audio-susceptibility transfer functions without and with feed-forward gains along with required power-stage transfer functions are derived for peak current-mode controlled PWM dc-dc buck converter. The derived audio-susceptibility transfer functions are illustrated for given values of perturbation ratio using MATLAB.

This paper presents the small-signal modeling of pulse-width modulated (PWM) Z-source converter (ZSC) operating in continuous conduction mode (CCM) by circuit averaging technique. The averaged large-signal, dc, and time-invariant linear small-signal circuit models of PWM ZSC power stage operating in CCM are derived. The small-signal modeling focuses on the dynamics introduced by the Z network present in the ZSC. Based on the small-signal model derived, the small-signal model required to derive the open-loop input-to-capacitor voltage transfer function is derived. The open-loop input-to-capacitor voltage transfer function is derived, and the associated theoretical Bode plots are illustrated using Matlab and is verified by circuit simulation. The theoretical results were in excellent agreement with the simulation results, validating the ac small-signal model and the derived input-to-capacitor voltage transfer function.

This paper presents a design procedure for the class F3RF power amplifier. The required range of the drain current conduction angle for the class F3power amplifier is specified. Additionally, an equation for the resistance of the third harmonic resonant circuit is given. Class F3, AB, and C power amplifiers were designed and simulated to compare their respective performance in terms of efficiency.

This paper introduces a zero voltage switching (ZVS) two-switch flyback pulse-width modulated (PWM) DC-DC converter along with the principle of circuit operation and steady-state analysis. The proposed converter topology is the result of incorporating an auxiliary circuit in place of the clamping diodes on the primary side of the conventional hard- switching two-switch flyback converter, resulting in a soft- switching two-switch flyback converter with reduced switch voltage stresses. The auxiliary circuit is an active-clamp circuit made up of two switches and a clamp capacitor. The active clamp circuit recycles the energy stored in the parasitic transformer leakage inductance, facilitates the ZVS operation of all active switches, and limits the voltage stresses of all the active switches to a value less than or equal to the DC input voltage VI. Circuit description, principle of operation, steady-state analysis, and simulation results of the proposed converter are presented.

This paper gives analytical expressions for the output power and the power conversion efficiency of the class-E power amplifier outside the class-E ZVS/ZDS switching conditions. The analytical predictions agreed with the experimental results quantitatively, which indicates the validity of the analytical expressions. Moreover, a design example applying the analytical expressions for the power conversion efficiency is given. By using the analytical expressions, it is possible to design the class-E amplifier, which improves the power conversion efficiency compared with that of the class-E amplifier satisfying the class-E ZVS/ZDS conditions.

The control-to-output and the duty ratio-to-inductor current transfer functions of peak current-mode controlled PWM dc-dc buck converter in CCM are derived and illustrated. The closed inner-current loop and the power stage inductor current-to-output voltage transfer functions are used to derive the control-to-output transfer function of the peak current-mode controlled buck converter in CCM, which is essential for the outer-voltage loop controller design. A small-signal model including parasitic components and delay is used to derive the power stage transfer function, necessary for proper analysis of the power stage. The loop gain of the inner-current loop is derived and is shown that it is independent of converter topology.

This paper introduces a two-switch flyback-forward pulse-width modulated (PWM) DC-DC converter along with the steady-state analysis, simplified design procedure, and experimental verification. The proposed converter topology is the result of integrating the secondary sides of the two-switch flyback and the two-switch forward converters in an anti-parallel connection, while retaining the two-main switches and the clamping diodes on a single winding primary side. The hybrid two-switch flyback-forward converter shares the semiconductor devices on the primary side and the magnetic component on the secondary side resulting in a low volume DC-DC converter with reduced switch voltage stress. Simulation and experimental results are given for a 10-V/30-W, 100 kHz laboratory prototype to verify the theoretical analysis.

Power efficiency of a class E RF power amplifier versus dc supply voltage VDDwhen the shunt capacitance of the class E amplifier is a nonlinear capacitance with the grading coefficient m = 0.5 is obtained. In the calculation of power efficiency, switching loss due to non-zero turning on of the MOSFET, power loss due to forward voltage drop of the MOSFET body diode, and power loss due to MOSFET on-resistance are incorporated. It is found that the highest power efficiency is obtained at a lower dc supply voltage than the designed dc supply voltage, even though the circuit was designed to achieve the nominal operation at the designed dc supply voltage. The calculation was performed with Mathcad programming and the results were verified with Pspice simulations.

In this paper, we present analytical expressions for the waveforms and design equations for achieving the ZVS/ZDS conditions in the class-E power amplifier, taking into account the gate-to-drain parasitic capacitance of the MOSFET. We also give a design example along with PSpice simulation and experimental results. The voltage waveforms obtained from both the PSpice simulation and the circuit experiment achieved the class-E ZVS/ZDS conditions completely, which verify the analytical expressions. The results in this paper indicate that it is important to consider the effect of the MOSFET gate-to-drain capacitance for achieving the class E ZVS/ZDS conditions. The experimental power conversion efficiency achieved 92.8 % at output power Po= 4.06 W and operating frequency f = 7 MHz.

This paper presents expressions for the limiting value of the duty cycle and the minimum value of the slope compensation for marginally stable operation as well as for the normalized crossover frequency, the maximum duty cycle, and the value of the slope compensation at a required phase margin. These quantities describe the performance of the inner-current loop in peak current-mode controlled PWM dc-dc converters. The derivations are based on the Pade approximation of z = exp(sTs). The results of this paper can be used for the design of the inner-current loop with a specified phase margin.

The class-E ZVS/ZDS operation within the class-DE amplifier can be easily achieved by adding external shunt capacitances. This paper presents the analytical expressions for the design of the class-DE amplifier with the shunt capacitances composed of the linear and nonlinear capacitances for the switch-on duty ratio D=0.25. In the analysis, an equivalent linear shunt capacitance of nonlinear MOSFET output capacitance are defined and derived. The analytical results show good agreement with the experimental ones, which validates our analysis.

A dynamic response of the output voltage to the input supply voltage VDDof a class E amplifier is derived with modeling the circuit by a low-frequency model and a high-frequency model. If the perturbation frequency is much lower than the switching frequency, the state-space averaging model of the class E amplifier can be approximated as a single-pole low-pass filter composed of the choke inductance LRFCand the parallel combination of the switch resistance and the shunt capacitor resistance. The analysis in this paper is based on the steady-state behavior outside the designed conditions given in. Hence, the derivation is applicable even if the class E amplifier is operated in off-tuned conditions. The analytical results for the frequency response of a 1 MHz class E amplifier matched well with Pspice simulations at the perturbation frequency less than 100 kHz.

The maximum operating frequency of the class E amplifier with nonlinear shunt capacitance depends on the transistor duty ratio. It varies with the duty ratio under zero-voltage switching (ZVS) and zero-derivative switching (ZDS) conditions at fixed values of the output power, dc supply voltage. Therefore, the design of the class E amplifier with given values of the shunt capacitance, the output power, dc supply voltage is possible by adjusting the operating frequency. The operating frequency has the maximum value when the duty ratio DONis approximately 0.36 at VDD/Vbi=1 . It is also shown that the maximum operating frequency is higher when the dc supply voltage VDDis lower.

Due to the nonlinearity of shunt capacitance of the class E amplifier, the output amplitude of the class E amplifier is not a linear function of the DC supply voltage of the class E amplifier. Estimating this nonlinearity is important to maintain ZVS operation in a situation of variable DC supply voltage, e.g., for a amplitude modulated (AM) power amplifier. However, there are no research results for the output amplitude of class E amplifier with nonlinear shunt capacitance. In this paper, the circuit behavior of the class E amplifier with nonlinear shunt capacitance outside designed nominal conditions is obtained using mathematical processing software MathCAD

This paper presents a circuit and a design of a CMOS zero cross-conduction low-power driver for an integrated synchronous buck converter. The circuit has a zero cross-conduction, yielding low-power dissipation and high efficiency. We used the Cadence design tool with 0.18 mum CMOS technology to implement and verify the functionalities of the low-power buck converter driver. The design criteria of these drivers depend on the power dissipation, delay, and physical size. The DC input voltage of this design is 1.2 V, the DC output voltage is 1 V, the output current is 120 mA, and the maximum operating frequency is up to 100 MHz. The total size of the driver is around 140 micron2plus the area of an inductor and a capacitor. The designed converter achieved the required specification, and its efficiency is up to 97.9%. This circuit is more efficient than other previous low-power buck converter drivers. The proposed circuit is better than Lee's et al. and our recent design in terms of efficiency, speed, and layout area. The new circuit is more than 4 times smaller than Lee's circuit. The circuit can be also used in I/O pads for high-current and low-power IC applications

In this paper, electronic ballast based on the class E oscillator with a capacitive impedance inverter is presented. The ballast allows us to supply an instant-start fluorescent lamp from a 12 V dc power source. The class E oscillator allows for increasing the efficiency using a simple structure with only one switch without a driving circuit. Due to the anti-parallel diode integrated into the switch, the ZVS condition is satisfied in the ignition mode, maintaining high efficiency. One of the applications of the ballast is mobile equipment, where compact independent power sources are used, for example, batteries or solar cells. The ballast was designed with the following parameters: VDD= 12 V, Po= 18 W, fo= 440 kHz. The measured efficiency was 83%, the output power was 18.5 W, and the dc supply power was 22.3 W at the operating frequency of 444.44 kHz

An analysis is given for sub-optimum conditions of class E amplifier with a nonlinear shunt capacitance with a grading coefficient of 0.5 at any duty cycle. By exploiting sub-optimum class E operation, various amplifier parameters such as input voltage, operating frequency, output power, and load resistance can be set as design specifications. An example of a design procedure of the class E amplifier is given. The theoretical results were verified with Pspice simulation using SPICE MOSFET model

A 12.5 mW, 500 MHz class DE power inverter was designed and simulated as an inverter part of dc-dc converters to realize a fully integrated switching power supply using a 1.2 mum CMOS process. A 20 nH spiral inductor was used in the resonant circuit. The class DE inverter requires lower inductance than PWM buck converter. Soft switching operation enables high conversion efficiency at high operating frequencies. The class DE inverter can be an excellent candidate for on-chip switching converters because of very high efficiency, smaller passive elements, and low peak switch voltage

A small-signal model for a PWM dc-dc boost converter operated in DCM composed of current-controlled current sources and derived by using the energy conservation approach is presented. The proposed model is suitable for small-signal, frequency-domain representation of the converter and can be used to derive the expressions and Bode plots of the control-to-output voltage transfer function. The input-to-output voltage transfer function, the input impedance, and the output impedance. Main advantages of the proposed method are as follows. A linear equivalent circuit of the converter is derived and its representation in the frequency domain given which does not require matrix manipulation. The converter parasitic components are considered. A good understanding of the frequency domain behavior of power converters is achieved. Finally, the proposed method can be easily utilized to model other PWM dc-dc converter circuits.

The small-signal closed-loop input impedance is derived for the PWM buck DC-DC converter operated in continuous conduction mode (CCM), taking into account all parasitic resistances. The plots of the closed-loop input impedance are shown versus frequency for four values of the equivalent series resistance of the capacitor.>