A highly efficient 2D convolutional algorithm based on the Discrete Hirschman Transform (DHT), known as DHT-Conv, has recently been developed. This method demonstrates superior performance compared to FFT-based convolution (FFT-Conv) in terms of computational complexity. In this paper, we implement DHTConv on Field Programmable Gate Arrays (FPGA) and evaluate its hardware performance on both Altera and Xilinx FPGA devices. The results from the Altera device indicate that our DHTConv significantly outperforms FFT-based convolution, yielding over 22% savings in real computations and approximately 5% in latency. Additionally, the results from the Xilinx FPGA board show that DHTConv requires fewer hardware resources compared to FFTConv, achieving over 16% savings in LUTs, 48% savings in flip-flops, and 61% savings in DSP blocks.

The Fast Fourier Transform (FFT)-based convolution is the most popular fast convolution algorithm. In past work, we developed the Discrete Hirschman Transform (DHT)-based convolution. When compared to the FFT-based convolution, our DHT-based convolution can reduce the computational complexity by a third. Recently, we developed a comprehensive DFT algorithm where every calculation is natively real-valued (RV) dot products. In this paper, we first apply the natively real-valued DFT to linear convolution. We call this method the RV-based convolution. The arithmetic analysis reveals that it efficiently reduces the operation counts. The algorithm is fast regardless of length.

Because mathematics classes are often taken at different locations, including high schools and 4-year schools, the math background of students in introductory electrical & computer engineering classes can vary significantly. We have addressed this by a careful restructuring of the circuits course “Intro to EE” taken by computer engineering students, as well as students in other non-EE majors. This course covers DC circuits, information circuits (filters), and AC circuits. These topics introduce material that is covered in multiple courses required for EE students. We have structured this course so that we cycle through analysis techniques for each type of circuit, which allows students to reinforce their previous knowledge. AC circuits are covered as a special case of information circuits. We have published an e-book that we have used for several years. The format of the e-book allows us to include video, interactive questions, and most importantly detailed examples that include even minor steps. We are exploring options for moving our textbook content to a standalone e-book to be used with a Learning Management System (LMS), such as canvas. The restructuring of the course to focus on fundamentals supports student success and early identification of weaknesses in math backgrounds.

With the best basis function that compactly describes a discrete-time signal, the Discrete Hirschman Transform (DHT) has been proved to perform better than the Discrete Fourier Transform (DFT) in terms of high resolution and computational complexity. It is reasonable to develop fast algorithms for the DHT computation since the DHT has applied to multiple signal processing applications. In this letter, we propose a split-radix DHT (SRDHT) including mathematical decomposition and comparison of computation complexity. The SRDHT is computationally superior to the DFT and performs more efficiently than our previously developed radix-2/-4 DHTs, with further reduced arithmetic operations. We regard this proposed SRDHT as a more attractive candidate to compute the DHT for those existing and future Hirschman-based applications.

The Discrete Hirschman Transform (DHT) is more computationally attractive than the Discrete Fourier Transform (DFT). Based on its derived linear convolution, we have confirmed that the DHT-based convolution filter shows its superiority in reducing computations conditionally, while compared with the conventional DFT-based convolution filter in our previous work. Since the DHT-based convolution has many configurations depending on parameter choices, we conjecture that there should be an optimal case for the largest reduction in computations. In this paper, for the DHT-based convolution, we express the requirement in real computations and propose an approach of how to determine the optimal parameters to reduce computations. We further compare the computational load of the optimal DHT-based convolution with that of other popular convolutions. Moreover, its reduction in clock cycles has also been estimated using a Digital Signal Processor (DSP) TMS320C5545. Results indicate that the optimal DHT-based convolution can reduce real computations (multiplications by 9.09%-50% and additions by 1.12%-51.09%) and clock cycles, according to the input length and filter size, except for some cases with identical performance to the radix-2 FFT-based competitor.

A Fast linear convolution algorithm based on the Discrete Hirschman Transform (DHT) provides increased hardware flexibility and reduced computational complexity compared to those based on the Fast Fourier Transform (FFT). This DHT convolution can be realized by block-processing filters. We propose a hardware-efficient structure to implement the DHT convolution filter. A digital data example is used to discuss its improvement in computational complexity. Observation indicates that our proposed DHT convolution filter either enjoys the same peak performances as its FFT competitor, or even reduces more computational load with a slightly larger output size. This performance can be further enhanced using alternative DHT-based methods.

Fast multiplication can be achieved by using canonical signed digit (CSD) to speed-up computations. Conversion to CSD is needed when the multiplier is not known a priori. In this work, a novel approach for converting an unsigned binary number or two's complement number to its CSD form from least significant bit to most significant bit, (right-to-left), is presented. Comparison shows that our algorithm is faster and requires less area than existing CSD conversion algorithms.

In this work we propose a graph based minimum adder depth algorithm for the multiple constant multiplication (MCM) problem. Hence, all multiplier coefficients are here guaranteed to be realized at the theoretically lowest depth possible. The motivation for low adder depth is that this has been shown to be a main factor for the power consumption. An FIR filter is implemented using different MCM algorithms, and the proposed algorithm result in 25% lower power in the MCM part compared to algorithms focused on minimizing the number of adders.

For finite impulse response (FIR) filter implementation, fixed point arithmetic is frequently used, where truncation or rounding can be applied to round 2n-bit products of 2 n-bit numbers to n-bit products internally for decreasing power dissipation and space cost. Also, the multiplication can be done multiplierlessly by using single constant multiplication (SCM) or multiple constant multiplication (MCM) algorithms. This paper proposes truncated MCM using pattern modification technique (PMT) for FIR filter implementation. Comparisons of PMT and UT (uniformly truncation) are made with FPGA-based simulations. Results show that the proposed PMT algorithm can meet FIR filter specifications, and reduce area cost by 35%, compared to non-truncated MCM algorithms, without increasing quantization error.

In this work, we propose a switching activity model for constant multipliers. The model can also be used for other architectures that are composed by full adders. Hence, the proposed model is suitable to be used in power consumption aware design algorithms. An important category is algorithms for the multiple-constant multiplication (MCM) problem. The model is shown to agree well with simulations, especially for carry-save arithmetic.

Adaptive filter implementations require real-time conversion of coefficients to canonical signed digit (CSD) or similar representations to benefit from multiplierless techniques for implementing filters. Multiplierless approaches are used to reduce the hardware and increase the throughput. This paper introduces a novel hardware implementation method that converts two's complement numbers to their CSD representations using a fixed number of shift and logic operations. As a result, we can greatly reduce the power consumption and area requirements for hardware implementation of DSP algorithms in which coefficients are not known a priori. Because all CSD digits are produced simultaneously, the conversion speed and thus the throughput are improved when compared to overlap-and-scan techniques such as Booth's recoding.

Implementation of digital signal processing (DSP) algorithms in hardware, such as field programmable gate arrays (FPGAs), requires a large number of multiplications. In this paper, we introduce a novel multiplier structure that converts from 2's complement to canonical signed digit (CSD) representation in real time. The proposed algorithm increases the number of zero partial products (which can be simplified by shift operations) to approximately 66.7% compared with 50% for modified Booth's recoding. Also, the proposed hardware structure reduces the non-zero partial products to a minimum, and consequently the number of arithmetic operations in the carry-save structure is reduced. So, our proposed hardware decreases both the time required for multiplication and the power consumption of the multiplier. Furthermore, because the proposed structure uses real time CSD recoding, and does not require a fixed value for the multiplier input to be known a priori, the proposed multiplier can be used to implement digital filters with non-fixed filter coefficients, such as adaptive filters.

Adaptive filtering is a widely used technique in active noise control (ANC). In order to make the adaptive filter in an FXLMS (filtered-x LMS) ANC system stable, the reference signal must pass through an estimation filter whose phase response is within /spl plusmn/90/spl deg/ of the phase of the secondary path. In this paper, we study the quantization effects on the filter phase response and the relationship between the phase response and the location of the zeros and poles. In addition, we propose a filter structure and nonuniform quantization method in which we quantize the filter coefficients so they each contain a small number of nonzero bits, based on the distance of the zeros/poles to the unit circle, to guarantee that the /spl plusmn/90/spl deg/ allowable phase deviation is met - greatly reducing the implementation cost. We combine these ideas with that of multiplierless implementations of adaptive FIR filters to realize an efficient active noise control using field programmable gate arrays or other digital hardware.

We propose a method for designing a filter to meet a set of specifications, which can be implemented with reduced area. Our approach combines a prefilter implementation structure whose function has been developed over the years with our previously reported variable precision technique for intelligently quantizing the filter coefficients. Our area-efficient structure uses frequency masking with a single filter model to give good performance with low order and low coefficient sensitivity. Our method does use a novel connection of a simple prefilter structure used in a frequency masking technique to give good designs for the previously unattainable wide-band filter designs. The technique also gives designs with superior (very sharp) transition regions. Both types produce filters that efficiently use digital circuitry, leading to space-efficient designs that are significantly smaller than would otherwise be the case. Some examples are given to demonstrate the effectiveness of our design.

We propose a method for designing a filter to meet a set of specifications, which can be implemented with reduced area. Our approach combines a prefilter implementation structure whose function has been developed over the years with our previously reported variable precision technique for intelligently quantizing the filter coefficients. Our area-efficient structure uses frequency masking with a single filter model to give good performance with low order and low coefficient sensitivity. Our method does use a novel connection of a simple prefilter structure used in a frequency masking technique to give good designs for the previously unattainable wide-band filter designs. The technique also gives designs with superior (very sharp) transition regions. Both types produce filters that efficiently use digital circuitry, leading to space-efficient designs that are significantly smaller than would otherwise be the case. Some examples are given to demonstrate the effectiveness of our design.

This paper introduces a sub-band adaptive algorithm that avoids the signal path delay, and so can be used in an adaptive active control (feedback) system. A side effect of this algorithm is that it still causes extra delay in the error path due to the analysis filter bank. Even though the delay along the error path has only a slight influence on the steady-state behavior, it does decrease the system bounds of stability. We propose an error path delay compensation method that alleviates this problem. Simulation results are presented to illustrate the efficiency of the new adaptive algorithm.

Reconfiguration for fault tolerance is a widely studied field, but this work applies graph grammars to this discipline for the first time. Reconfiguration Graph Grammars (RGG) are defined and applied to the definition of processor array reconfiguration algorithms. The nodes of a graph are associated with the processors of a processor array, and the edges are associated with those interprocessor communication lines that are active. The resulting algorithms for dynamic (run-time) reconfiguration are efficient and can be implemented distributively.

This paper describes the use of a new, multiple use laboratory facility in DSP education at the University of Oklahoma. The facility, funded by a combination of NSF grant money, industrial donations and university funds supports the teaching of signal and image processing, telecommunications and multimedia courses. This unique combination of related areas has fostered significant faculty and department interaction to support the strong telecommunications industry in the region. In fact, the laboratory was chosen as the model laboratory for the joint OU/OSU program in Telecomputing.