Abstract---Static timing analysis of VLSI circuits relies on tabular models of logic gates obtained during library characterization. At characterization time logic gates are simulated at the circuit level with a range of input waveforms (e.g., saturated ramps with different slews) and various output loads. At timing analysis time the same gates are driven by input waveforms that differ from the class of characterization waveforms. This paper proposes a method for mapping the waveforms that arise in static timing analysis to members of the class of waveforms used to characterize gate timing performance during library characterization. The method is based on the moments of the input waveform, which describe concisely the salient features of the waveform. The mapping between the input waveform and the effective characterization waveform is accomplished by positing functional relationships between the input waveform’s moments and the parameters of the characterization waveform. The unknown coefficients of this functional relationship are determined by minimizing the worst case error of the output waveform over a representative set of input waveforms and gate loads. The technique requires no change to the library characterization procedure, and minimal change to the static timing tool with little to no additional computational burden on the timer.

This paper describes a new design methodology to analyzethe on-chip power supply noise for high-performance microprocessors.Based on an integrated package-level andchip-level power bus model, and a simulated switching circuitmodel for each functional block, this methodology offersthe most complete and accurate analysis of Vdd distributionfor the entire chip. The analysis results not only providedesigners with the inductive ΔI noise and the resistive IRdrop data at the same time, but also allow designers to easilyidentify the hot spots on the chip and ΔV across the chip.Global and local optimization such as buffer sizing, powerbus sizing, and on-chip decoupling capacitor placement canthen be conducted to maximize the circuit performance andminimize the noise.

CAD tools and research in the area of reduced-ordermodeling of large linear interconnect networks have evolvedfrom merely finding a Pad' e approximation for the givennetwork transfer function to finding an approximate transferfunction that preserves such circuit-theoretic propertiesof the network as stability, passivity, and RLC synthesizability.In particular, preserving passivity guarantees thatthe reduced-order models will be well-behaved when embeddedback in the circuit where the interconnect networkoriginated. While stability can be ascertained by studyingthe poles of the reduced-order transfer function, passivitydepends on both the poles and zeros of the networkdriving-point impedance. In this paper, we present a novelmethod for studying the zeros of reduced-order transferfunctions and show how it yields conclusions about passivityand synthesizability. Moreover, in order to obtain aguaranteed-passive reduced-order model for multiport RCnetworks, a new algorithm based on the Arnoldi iteration ispresented. This algorithm is as computationallyefficient asthe one used to generate guaranteed-stable reduced-ordermodels [Coordinate-transformed Arnoldi for generating guranteed stable reduced-order models for RLC circuits].

Work in the area of model-order reduction for RLC interconnect networks has focused on building reduced-order models that preserve the circuit-theoretic properties of the network, such as stability, passivity, and synthesizability (Silveira et al., 1996). Passivity is the one circuit-theoretic property that is vital for the successful simulation of a large circuit netlist containing reduced-order models of its interconnect networks. Non-passive reduced-order models may lead to instabilities even if they are themselves stable. We address the problem of guaranteeing the accuracy and passivity of reduced-order models of multiport RLC networks at any finite number of expansion points. The novel passivity-preserving model-order reduction scheme is a block version of the rational Arnoldi algorithm (Ruhe, 1994). The scheme reduces to that of (Odabasioglu et al., 1997) when applied to a single expansion point at zero frequency. Although the treatment of this paper is restricted to expansion points that are on the negative real axis, it is shown that the resulting passive reduced-order model is superior in accuracy to the one that would result from expanding the original model around a single point. Nyquist plots are used to illustrate both the passivity and the accuracy of the reduced order models.

Article Free Access Share on Efficient full-wave electromagnetic analysis via model-order reduction of fast integral transforms Authors: Joel R. Phillips MIT Department of EECS, Cambridge, MA MIT Department of EECS, Cambridge, MAView Profile , Eli Chiprout IBM Research Laboratory for Advanced Microprocessor Design, Austin, TX and IBM T. J. Watson Research Center, Yorktown Heights, NY IBM Research Laboratory for Advanced Microprocessor Design, Austin, TX and IBM T. J. Watson Research Center, Yorktown Heights, NYView Profile , David D. Ling IBM T. J. Watson Research Center, Yorktown Heights, NY IBM T. J. Watson Research Center, Yorktown Heights, NYView Profile Authors Info & Claims DAC '96: Proceedings of the 33rd annual Design Automation ConferenceJune 1996 Pages 377–382https://doi.org/10.1145/240518.240590Published:01 June 1996Publication History 39citation410DownloadsMetricsTotal Citations39Total Downloads410Last 12 Months11Last 6 weeks3 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

A description is given of C3DSTAR, a capacitance program for three-dimensional configurations of conductors and dielectrics, that incorporates a hybrid integral-equation solution of the capacitance problem. The hybrid method combines the use of multilayer Green's function treatment of the infinite planar dielectric interfaces with an explicit treatment of the bound charge at finite and/or irregular dielectric interfaces. The approach described differs from previous hybrid integral equation methods in that the free charge density is the primary unknown, rather than the total charge density. This allows early elimination of numerically induced asymmetry in the capacitance matrix and results in more accurate capacitive values.>