Demo Data from EDBT 2026 / reviewers in the wild / expert
John A. DeRosa
dblp:36/4630
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1987
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 87% Performance modeling and evaluation · 13% |
Topics — the 2 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Processor architecture and microarchitecture › pipelining
delayed branch |
0.0 | 1 | 1987 | An Evaluation of Branch Architectures · ISCA 1987 |
Processor architecture and microarchitecture
instruction set architecture |
0.0 | 1 | 1987 | An Evaluation of Branch Architectures · ISCA 1987 |
Methods — techniques the papers use, named apart from their topics
simulation · 0.0analytical modeling · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1987 | An Evaluation of Branch ArchitecturesabstractBranch instructions form a significant fraction of executed instructions, and their design is thus a crucial component of any architecture. This paper examines three alternatives in the design of branch instructions: delayed vs. non-delayed branches, one- vs. two-instruction branches, and the use or non-use of condition codes. Simulation and analytical techniques are used to provide quantitative comparisons between these choices. John A. DeRosa, Henry M. Levy |
ISCA | 1 |