This paper presents two designs of digitally controlled ring oscillators (DCRO) using SRAM-inspired cells in a commercially available 22 nm technology node. The proposed design offers a compact, compilable, DCRO capable of rapid transition between digitally selectable frequencies. Two designs are conducted on a commercially available 22 nm technology node, a compact minimal footprint design occupying 25.58μm2area (Design-I) and a scaled up design occupying 50.5μm2(Design-II). Extensive simulations validate low transit time between frequency-states (≤15ns on post-extracted netlists), while offering a tuning range of 700 MHz and 1.736 GHz for Design-I and Design-II respectively. Design-I performs competitively with state-of-the-art ring oscillators, consuming 42.5 μW from a 0.8 V supply while achieving a figure of merit (FoM) of 144.79 dBc/Hz for a 1.05 GHz frequency, While Design-II, consuming − 83.8 μW from a 0.8 V supply demonstrates an of –174.01 dBc/Hz for a 1.92 GHz local oscillator signal. This outperforms existing freerunning oscillators, delivering results competitive with those achieved using a PLL.

This paper describes design techniques for ultra-low power cryogenic CMOS circuits for next generation quantum computing applications. Specifically, it discusses two generations of fully integrated analog front-end circuits realized using end-to-end current mode design techniques to realize RF control of qubits at 4K ambient temperatures, presenting design The demonstrated current mode qubit state controller designs were implemented in 14nm FinFET CMOS technology; these designs consume 23.1mW and 12.8mW respectively.

This paper presents predictive techniques that suggest a path to accelerated analysis and optimization of the yield of ultra-low power analog/mixed signal designs operating at cryogenic temperatures for use in future quantum computing applications. Analysis of 6σ variation is accelerated using mixture importance sampling (MixIS) techniques, with key studied specifications being compliance to spurious tone requirements at the quantum state controller output and optimization of design power consumption, both in the context of the high levels of modeling and matching uncertainties associated with cryogenic circuit design.

Future generations of quantum computers are expected to operate in a paradigm where multi-qubit devices will predominantly perform circuits to support quantum error correction. Highly integrated cryogenic electronics are a key enabling technology to support the control of the large numbers of physical qubits that will be required in this fault-tolerant, error-corrected regime. Here, we describe our perspectives on cryoelectronics-driven qubit control architectures, and will then describe an implementation of a scalable, low-power, cryogenic qubit state controller that includes a domain-specific processor and a SSB upconversion I/Q-mixer-based RF AWG. We will also describe an FPGA-based emulation platform that is able to closely reproduce the system intention, and which was used to verify different aspects of the ASIC system design in in situ transmon qubit control experiments.

In this paper, for the first time, the phase noise analysis of a Multi-loop Skew based Single Ended Oscillator (MSSROs) is derived and validated. Compared to the three stages of conventional ring oscillators (CROs), SDROs provide an equivalent oscillation frequency with improved phase noise with increasing stages. The primary distinction between these two designs (SDRO and three-stage CROs) is the inherent skew offset between the PMOS/NMOS gates caused by the unique connection. This skew offset is the fundamental cause of delay cell noise suppression; the SDROs have loosely coupled oscillators that run concurrently, forming multiple 3-stages of separately driven Ring Oscillators. As a result, a shaping function is derived in terms of skew offset, and simulating these with varying skew offset results in suppressing behavior. Additionally, we derived phase noise for a skew-based design and validated it in PDKs of 180nm and 65 nm. We plotted the thermal (flicker) noise contribution and found that increasing the number of stages leads to an approximately 1-2 dB reduction in phase noise while maintaining the same NMOS/PMOS size ratio. Finally, a 2-3 dB reduction in phase noise is achieved in MSSROs by incorporating the shaping function into phase noise equations.

An all-digital phase interpolator (PI)-based clock and data recovery (CDR) is proposed in this paper to accommodate any data rate continuously from 1 to 16 Gb/s with quadrature sampling clocks from 4 to 8 GHz. A new low-power two-step PI (TSPI) with high linearity over 4-8 GHz range is presented. The all-digital CDR control loop adopts a multimode phase detection scheme enabling continuous data rate support. The digital architecture not only eliminates the large filtering capacitor but also makes the design more tolerant to process, voltage, and temperature variations. The CDR core occupies 0.088 mm2in a commercial 65-nm CMOS technology and consumes 73.1 mA at 16 Gb/s from a 1.2 V power supply. The differential nonlinearity of the PI is measured to be within 0.48 LSB. The measurement results show that this CDR can function at the proposed phase detection modes and is able to exceed the synchronous optical networking (SONET) OC-192 jitter tolerance mask at least by 0.2 unit interval at high frequencies (4-100 MHz) with a 231- 1 pseudorandom binary sequence data pattern at 10 Gb/s and a target bit error rate of 10-12.

This paper presents a low-power 10-Gb/s vertical cavity surface emitting laser (VCSEL) driver integrated circuit (IC) with electrostatic discharge (ESD) protection in the 130-nm CMOS technology. A distributed amplifier (DA)-based modulator is proposed to boost the driver bandwidth. It employs artificial transmission lines to cancel the device parasitic capacitances of the driver. A distributed ESD protection technique is applied to equalize the group delay of the DA to optimize the jitter performance. To minimize the silicon area, the optimal number of DA taps in the proposed modulator has been derived. To compensate for the capacitive load and the channel losses at the output of the driver, a frequency-domain preemphasis scheme is proposed. The proposed DA modulator occupies an area of 0.69 mm2, and the entire driver IC has a die size of 2 mm×2 mm, including the pads. Both electrical and optical tests have been carried out to characterize the performance of the proposed VCSEL driver IC. Measurements at a data rate of 10-Gb/s demonstrate a typical power consumption of 85 mW under a single 2.5 V supply voltage (49 mW, if separate 1.2 and 2.5 V supplies are used) and an rms jitter of 0.63 and 1.12 ps for the electrical test and optical test, respectively.