The electronics industry is increasingly focused on the consumer marketplace, which requires low-cost high-volume products to be developed very rapidly. This, combined with advances in deep submicrometer technology have resulted in the ability and the need to put entire systems on a single chip. As more of the system is included on a single chip, it is increasingly likely that the chip will contain both analog and digital sections. Developing these mixed-signal (MS) systems-on-chip presents enormous challenges both to the designers of the chips and to the developers of the computer-aided design (CAD) systems that are used during the design process. This paper presents many of the issues that act to complicate the development of large single-chip MS systems and how CAD systems are expected to develop to overcome these issues.

This work examines the practical issues concerning the realization of switched-capacitors video-rate finite-impulse response filters based on standard CMOS technology. The capacitor spread/sensitivity tradeoff is explored for a number of architectural solutions and an architecture suitable to the challenges of the video field is identified. The nonidealities of switches and operational amplifiers, which must be accounted for at video-rate, are analyzed and practical solutions to prevent performance deterioration are proposed. The implementation of a concrete design case is discussed and presented as a demonstration of the technological solutions proposed.

The problem of designing complex analog circuits is attacked using a hierarchical top-down, constraint-driven design methodology. In this methodology, constraints are propagated automatically from high-level specifications to physical design through a sequence of gradual transformations. Constraint transformation is a critical step in the methodology, since it determines in large part the degree to which specifications are met. In this paper we describe how constraint transformations can be efficiently carried out using hierarchical parameter modeling and constrained optimization techniques. The process supports complex high-level specification handling and accounts for second-order effects, such as interconnect parasitics and mismatches. The suitability of the approach is demonstrated through an 4 th order active filter test case.

A novel constraint-graph algorithm for the optimization of yield is presented.This algorithm improves the yield of a layout by carefully spacing objects to reduce the probability of faults due to spot defects.White space b etween objects is removed and spacing in tightly packed a r e as of the layout is increased.The computationally expensive problem of optimizing yield is transformed into a network ow problem, which can be solved via known ecient algorithms.Yield can be improved either without changing the layout area, or if necessary by increasing the layout area to maximize the number of good chips per wafer.Our method c an in theory provide the best possible yield achievable without modifying the layout topology.The method is able to handle a general class of convex objective functions, and can therefore optimize not only yield, but other circuit performance functions such as wire-length, cross-talk and power.

A novel methodology for circuit design and automatic layout generation is proposed for a class of mixed-signal circuits in presence of layout parasitics and substrate induced noise.Accurate and efficient evaluation of the circuit during design is possible by taking into account such non-idealities.Techniques are presented to derive and use a set of constraints on substrate noise and on the geometric instances of the layout.Verification is performed using substrate extraction in combination with parasitic estimation techniques.To show the suitability of the approach, a VCO for a PLL has been designed and implemented in a CMOS 1m technology.The circuit has been optimized both at the schematic and at the layout level for power and performance, while its sensitivity to layout parasitics and substrate noise has been minimized.

In a constraint-driven layout synthesis environment, parasitic constraints are generated and implemented in each phase of the design process to meet a given set of performance specifications. The success of the synthesis phase depends in great part on the effectiveness and the generality of the constraint generation process. None of the existing approaches to the constraint generation problem however are suitable for a number of parasitic effects in active and passive devices due to non-deterministic process variations. To address this problem a novel methodology is proposed based on the separation of all variables associated with non-deterministic parasitics, thus allowing the translation of the problem into an equivalent one in which conventional constrained optimization techniques can be used. The requirements, of the method are a well-defined set of statistical properties for all parasitics and a reasonable degree of linearity of the performance measures relevant to design.

A methodology for the automatic synthesis of full-custom IC layout with analog constraints is presented. The methodology guarantees that all performance constraints are met when feasible, or otherwise, infeasibility is detected as soon as possible, thus providing a robust and efficient design environment. In the proposed approach, performance specifications are translated into lower-level bounds on parasitics or geometric parameters, using sensitivity analysis. Bounds can be used by a set of specialized layout tools performing stack generation, placement, routing, and compaction. For each tool, a detailed description is provided of its functionality, of the way constraints are mapped and enforced, and of its impact on the design flow. Examples drawn from industrial applications are reported to illustrate the effectiveness of the approach.

An algorithm for the automatic generation of full-stacked layouts in CMOS analog circuits is described in this paper. The set of stacks obtained is optimum with respect to a cost function which accounts for critical parasitics and device area minimization. Device interleaving and common-centroid patterns are automatically introduced when possible, and all symmetry and matching constraints are enforced. The algorithm is based on operations performed on a graph representation of circuit connectivity, exploiting the equivalence between stack generation and path partitioning in the circuit graph. Path partitioning is carried out in two phases: in the first phase, all paths are generated by a dynamic programming procedure. In the second phase, the optimum partition is selected by solving a clique problem. Original heuristics have been introduced, which preserve the optimality of the solution, while effectively improving the computational efficiency of the algorithm. The algorithm has been implemented in the "C" programming language. Many test cases have been run, and the quality of results is comparable to that of hand-made circuits. Results also demonstrate the effectiveness of the heuristics employed, even for relatively complex circuits.>

Switched-capacitor technology implemented by 2.4 /spl mu/m CMOS offers considerable reliability/cost advantages. Its limited clock-rate values are the traditional obstacle to its introduction in high frequency applications, such as video. This obstacle can be removed by an architectural scheme broadening the internal clock rate by an integer factor with respect to the input clock rate. The feasibility of this concept is demonstrated by the switched-capacitor realization of a color difference prefilter complying with Recommendation CCIR 601.>

New placement techniques are presented which substantially improve the process of automatic layout generation of analog IC's. Extremely tight specifications can be enforced on high-performance analog circuits by using simultaneous placement and module optimization. An algorithmic approach to module generation provides alternative sets of modules optimized with respect to area and performance but equivalent in terms of parasitics and topology. The final module selection is performed during the placement phase, based on Simulated Annealing. The flexibility of the annealing algorithm has been significantly improved, thus making it possible to more efficiently exploit the tradeoffs between area, parasitics and matching.

A general methodology is presented for the generation of a complete set of constraints on interconnect parasitics, parasitic mismatch and on the physical topology of analog circuits. The parasitic and matching constraints are derived from high-level performance specifications by means of sensitivity analysis in time and frequency domain using quadratic optimization. Topological constraints are obtained by using sensitivity and matching information on devices and interconnect as well as graph-based techniques to extract the necessary geometric information.

An area router specifically tailored for the layout of analog circuits is presented. It is based on the A* algorithm, which combines the flexibility of maze routing with computational efficiency. Parasitics are controlled by means of a programmable cost function based on a set of user-defined weights. The weights can be automatically defined based on high-level electrical performance specifications and determine the net scheduling. An algorithm for symmetric routing preserves symmetries in differential architectures. Different current paths can be dealt with in each wire by means of a net partitioning procedure driven by information on the current driven by terminals. Shields can be built between critically coupled wires, in order to guarantee an effective limitation of cross-coupling. The weight-driven programmable cost function makes this router particularly suitable for a performance-driven approach to analog routing. Automatic weight definition also makes the use of the tool independent of the user's expertise. The implemented algorithms are described, and results proving the effectiveness of this approach are given.>

A general methodology for the design of the interconnections of analog circuits to meet high-level constraints on performance is described. In this approach, sensitivities of performance to parasitics are computed, and a set of bounding constraints for parasitics is determined. Sensitivities are then used to generate the weights for a cost function-driven analog area router. After the routing is completed, the actual values of critical parasitics are used to check if the user-defined constraints on circuit performance are met. If the requirements have not been satisfied, the bounding constraints generated on the parasitics are used to increase the weights associated with the parasitics which violated the constraints, and the circuit is rerouted. Results validating the effectiveness of this approach for layout-design automation of analog circuits are reported.>