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Noboru Okuda

dblp:36/5095 · DBLP profile ↗
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4ranked-venue papers
0as first author
0since 2021 · last 1982
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
4 papers
Electronic design automation · 91% Integrated circuit design · 9%

Topics — the 10 heaviest of 11, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
physical design		 0.041982
A placement algorithm for polycell LSI and ITS evaluation · DAC 1982
A Layout System for the Random Logic Portion of an MOS LSI Chip · IEEE Trans. Computers 1981
SHARPS: A hierarchical layout system for VLSI · DAC 1981
Electronic design automation › physical design
layout system		 0.021981
SHARPS: A hierarchical layout system for VLSI · DAC 1981
A layout system for the random logic portion of MOS LSI · DAC 1980
Electronic design automation › physical design
placement		 0.011982
A placement algorithm for polycell LSI and ITS evaluation · DAC 1982
Electronic design automation › physical design
routing		 0.011982
A placement algorithm for polycell LSI and ITS evaluation · DAC 1982
Electronic design automation › physical design › layout analysis
hierarchical layout analysis		 0.011981
SHARPS: A hierarchical layout system for VLSI · DAC 1981
Electronic design automation › physical design
placement and routing		 0.011981
A Layout System for the Random Logic Portion of an MOS LSI Chip · IEEE Trans. Computers 1981
Electronic design automation › physical design
VLSI layout		 0.011981
A Layout System for the Random Logic Portion of an MOS LSI Chip · IEEE Trans. Computers 1981
Integrated circuit design
digital circuit design		 0.011981
A Layout System for the Random Logic Portion of an MOS LSI Chip · IEEE Trans. Computers 1981
Integrated circuit design › large-scale integration
MOS LSI		 0.011981
A Layout System for the Random Logic Portion of an MOS LSI Chip · IEEE Trans. Computers 1981
Integrated circuit design
VLSI design		 0.011981
SHARPS: A hierarchical layout system for VLSI · DAC 1981

Methods — techniques the papers use, named apart from their topics

optimization heuristics · 0.0iterative improvement · 0.0hierarchical layout · 0.0heuristic optimization · 0.0
YearPublicationVenuePosition
1982 A placement algorithm for polycell LSI and ITS evaluation
Takashi Kambe, Toru Chiba, Seiji Kimura, Tsuneo Inufushi, Noboru Okuda, Ikuo Nishioka
 DAC5
1981 SHARPS: A hierarchical layout system for VLSI
Toru Chiba, Noboru Okuda, Takashi Kambe, Ikuo Nishioka, Tsuneo Inufushi, Sieji Kimura
 DAC2
1981 A Layout System for the Random Logic Portion of an MOS LSI Chip
abstract
The random logic portion of an MOS LSI chip intended mainly for a calculator is constructed of an array of MOS complex gates, each composed of an MOS ratioless circuit with a multiphase clocking system, and occupies ordinarily a considerable part of chip area. In this paper a layout system for this portion of an LSI chip is described, which is constructed on the basis of heuristics for a set of interrelated optimization problems. Implementation results of the layout system are also shown to reveal that the random logic portion can be realized in such an areas as comparable to one done by manual layout.
Isao Shirakawa, Noboru Okuda, Takashi Harada, Sadahiro Tani, Hiroshi Ozaki
 IEEE Trans. Computers2
1980 A layout system for the random logic portion of MOS LSI
abstract
The random logic portion of an MOS LSI chip intended mainly for a calculator is constructed of an array of MOS complex gates, each composed of an MOS ratioless circuit with a multi-phase clocking system, and occupies ordinarily a considerable part of chip area. In this paper, a layout system for this portion of an LSI is described, which is constructed on the basis of a set of optimization heuristics. Experimental results of the layout system are also shown so as to reveal that the random logic portion can be realized in much the same area as can be done by manual layout.
Isao Shirakawa, Noboru Okuda, Takashi Harada, Sadahiro Tani, Hiroshi Ozaki
 DAC2