We present a self-repairing circuit for a mesh-connected processor array with faulty processing elements which are directly replaced by spare processing elements on two orthogonal lines at the edges of the array. First, the spare assignment problem is formalized as a matching problem in graph theory. Using the result, we present an algorithm for reconstructing the array in a convenient form for finding the matching by a logical circuit. Second, the logical circuit which exactly realizes the algorithm is given. The circuit can be embedded in a target processor array to reconstruct very quickly the array with faulty processing elements without the aid of a host computer. This implies that the proposed system is effective in enhancing especially the run-time reliability of a processor array.

For a redundant (array) system, he (or she) who considers that the total system reliability might be worse than a nonredundant system because of additional circuit faults might naturally say, "Is the redundancy really useful?". The main purpose of the paper is to answer the question for redundant array systems using E-1 1/2 track switches (Tadayoshi Horita and Itsuo Takanami, 2000) and a reconfiguration method. The answer is "the redundancy using these methods is useful!". Furthermore, the condition that the assumption that additional circuits such as tracks, switches, etc. are fault-free becomes valid is given.

A mesh-connected processor array consists of many similar processing elements (PEs) which can be executed in both parallel and pipeline processing. For the implementation of an array of large numbers of processors, some fault-tolerant issues are necessary to enhance the (fabrication-time) yield and the (run-time) reliability. In this paper, we propose a fault-tolerant reconfigurable processor array using single-track switches like Kung et al.'s model. The reconfiguration process in our model is executed based on the concept of the "compensation path" like Kung et al.'s method, too. In our model, spare PEs are not necessarily put around the array, but are more flexibly put in the array by changing connections between spare PEs and nonspare PEs while retaining the connections among nonspare PEs in the same manner in Kung et al.'s model. The proposed model has such a desirable property that physical distances between logically adjacent PEs in the reconfigured array are within a constant, that is, independent of sizes of arrays. We show that the hardware overhead of the proposed model is a little greater than that of Kung et al.'s model, while the yield of the proposed model is much better than that of Kung et al.'s model.