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Xingjian Zhang 0005

dblp:36/5276-5 · DBLP profile ↗
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3ranked-venue papers
1as first author
3since 2021 · last 2024
0000-0001-8009-0242ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021Security and privacy · 1 · 1 first-author · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Network and information security
3 papers
Hardware security and side channels · 43% Systems and software security · 38% Web and mobile security · 19%
Computer architecture, parallel and distributed computing, and storage systems
2 papers
Memory systems · 65% Processor architecture and microarchitecture · 35%

Topics — the 8 heaviest of 9, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware security and side channels › side-channel attack
cache side-channel attacks
0.812024
RECAST: Mitigating Conflict-Based Cache Attacks Through Fine-Grained Dynamic Mapping · IEEE Trans. Inf. Forensics Secur. 2024
Hardware security and side channels › side-channel attack › cache side-channel attacks
conflict-based cache attacks
0.812024
RECAST: Mitigating Conflict-Based Cache Attacks Through Fine-Grained Dynamic Mapping · IEEE Trans. Inf. Forensics Secur. 2024
Systems and software security › vulnerability discovery
fuzzing
0.812024
Automated Data Binding Vulnerability Detection for Java Web Frameworks via Nested Property Graph · ISSTA 2024
Systems and software security
vulnerability discovery
0.812024
Automated Data Binding Vulnerability Detection for Java Web Frameworks via Nested Property Graph · ISSTA 2024
Memory systems
cache
0.812024
RECAST: Mitigating Conflict-Based Cache Attacks Through Fine-Grained Dynamic Mapping · IEEE Trans. Inf. Forensics Secur. 2024
Processor architecture and microarchitecture › hardware-assisted security
cache side channel defense
0.812024
RECAST: Mitigating Conflict-Based Cache Attacks Through Fine-Grained Dynamic Mapping · IEEE Trans. Inf. Forensics Secur. 2024
Memory systems
oblivious RAM
0.712023
Hitchhiker: Accelerating ORAM With Dynamic Scheduling · IEEE Trans. Computers 2023
Hardware security and side channels › side-channel countermeasures
memory access pattern protection
0.212023
Hitchhiker: Accelerating ORAM With Dynamic Scheduling · IEEE Trans. Computers 2023

Methods — techniques the papers use, named apart from their topics

tweakable index randomization · 1.5address-sensitive secret generation · 1.5level-grained scheduling · 1.3dynamic scheduling · 1.3static analysis · 0.8nested property graph · 0.8bind-site instrumentation · 0.8
YearPublicationVenuePosition
2024 Automated Data Binding Vulnerability Detection for Java Web Frameworks via Nested Property Graph
abstract
Data binding has been widely adopted by popular web frameworks due to its convenience of automatically binding web request parameters to the web program's properties. However, its improper implementation in web frameworks exposes sensitive properties, leading to data binding vulnerabilities, which can be exploited to launch severe attacks, such as the Spring4Shell remote code execution. Despite their criticalness, these issues are overlooked, and there is no systematic study addressing them. This paper presents the first automatic analysis of the data binding vulnerabilities in Java web frameworks. We develop an automatic Data bInding Vulnerabilities dEtectoR, named DIVER, to analyze data binding vulnerabilities. DIVER employs three new techniques: the Nested Property Graph-based Extraction to extract nested properties, the Bind-Site Instrumentation-based Identification to identify bindable nested properties, and the Property-aware Fuzzing to trigger and detect data binding vulnerabilities. We evaluated DIVER on two widely used Java web frameworks, Spring and Grails, and discovered 81 data binding vulnerabilities. These vulnerabilities can be exploited to launch remote code execution, arbitrary file read, and denial of service attacks. We have responsibly reported these vulnerabilities to the corresponding teams and helped to fix them. Three new CVEs with critical and high severity ratings have been assigned to us, including the infamous Spring4Shell.
Xiaoyong Yan, Biao He 0002, Wenbo Shen, Yu Ouyang, Kaihang Zhou, Xingjian Zhang 0005, Yukai Cao
ISSTA6
2024 RECAST: Mitigating Conflict-Based Cache Attacks Through Fine-Grained Dynamic Mapping
abstract
Conflict-based cache attacks can leak critical information from target programs. Accordingly, randomization-based cache designs have emerged as an efficient and LLC-favorable way to mitigate such attacks. However, later investigations have revealed several problems with these designs. Specifically, we identify limited randomness and coarse-grained protection as key issues of previous designs. To solve these issues, we proposeRecast, a secure cache design with address-sensitive secret generation and tweakable index randomization. Our insight is that cache modules at different levels can work collaboratively to enhance their security. Address-sensitive secret generation in private caches generates a secret value for each address upon cache misses. The shared cache in Recast uses tweakable index randomization, where the cryptographic function uses the secret value from private caches as the input to calculate the cache set index. Therefore, Recast achieves fine-grained dynamic mapping. We implement Recast in the gem5 simulator. We use a micro-benchmark and a benchmark suite to showcase the security of Recast. Our performance evaluations on SPEC 2017 and PARSEC benchmarks show that Recast incurs 2.29% and 2.03% performance overhead. Moreover, Recast with the LRU replacement policy has only 0.51% and 1.04% performance overhead on the two benchmarks. Therefore, Recast provides higher security guarantees with minimal performance overhead.
Xingjian Zhang 0005, Haochen Gong, Yajin Zhou
IEEE Trans. Inf. Forensics Secur.1
2023 Hitchhiker: Accelerating ORAM With Dynamic Scheduling
abstract
Oblivious RAM (ORAM) remains a bittersweet protection of memory access patterns because of its prohibitively high overhead. The root cause is that ORAM hides intended accesses among a sufficiently large number of dummy accesses. Most existing optimizations mitigate memory accesses using architectural enhancements (e.g., cache) yet few of them improve the efficiency of ORAM primitives per se. In this paper, we identify path-grained static scheduling as a fundamental ORAM performance bottleneck. We propose level-grained dynamic scheduling that directly optimizes ORAM primitives to boost efficiency. It enables ORAM to service more than one request per path and write paths batch wise. We can thus boost ORAM efficiency through handling queued requests as soon as possible and remove as many redundant accesses as possible. Since optimized memory accesses still target the same set of paths, dynamic scheduling preserves ORAM security. We implement dynamic scheduling through Hitchhiker ORAM. In comparison with the state-of-the-art primitive-optimized Fork Path ORAM, Hitchhiker ORAM yields 31.5% fewer memory accesses, 60.2% shorter latency, and 40.7% less energy consumption, being 2.5× faster. In comparison with the state-of-the-art architecture-optimized$\rho$, Hitchhiker ORAM is 1.5× faster and the integrated version—$\rho$-Hitchhiker ORAM is 2.0× faster.
Jingsen Zhu, Mengming Li, Xingjian Zhang 0005, Kai Bu
IEEE Trans. Computers3