This paper presents an innovative integrated load-pull bench at 160 GHz. The proposed system, which is designed in a 55-nm BiCMOS technology, is tailored to deal with all of the measurement functions including signal generation, shaping, and magnitude and phase measurement. This system will allow precise characterization of Devices-Under-Test (DUTs) (i.e., circuits and/or devices) when integrated together with the DUT. In addition, the proposed system could also be envisioned as a System-on-Chip (SoC) that, when reported into an RF probe, could serve as a test bench for any integrated circuit.

Integrated LDOs are closed loop systems; characterization of their gain and bandwidth is critical. Generally, gain and bandwidth parameters are extracted from LDO design simulations. However, LDO loop parameter testing requires breaking the loop and injecting a test signal into the IC. This paper presents test bed simulations and new test techniques for direct on-chip vectorless measurement of LDO DC loop gain and bandwidth. The LDO can be easily configured into two different test modes to measure these parameters. In test mode I, an additional op-amp is used as an integrator and is connected to the LDO control loop in a feedback servo loop. This forces a null at the LDO error amplifier input and simplifies DC gain measurements. The second amplifier stabilizes the DC operating point of the LDO pass transistor and error amplifier when the control loop is broken. Maintaining and controlling normal DC operating conditions is essential when measuring control loop parameters. Initial simulation results show that this approach maintains LDO component DC operating points and the LDO DC loop gain is measured with high accuracy. In test mode II, the LDO core is configured as an oscillator. The oscillation frequency can be used to estimate the bandwidth of the LDO and can be evaluated to monitor component faults. The Design for testability (DFT) technique to configure the LDO into these test modes is presented and the related practical problems and limitations are discussed.This new test technique has been applied to measure a working LDO test IC developed in a 65nm CMOS UMC technology. The simulation and practical implementation results show close agreement and the proposed test techniques can be practically integrated in a BIST structure.

In this paper, the authors propose an on-die power supply noise measurement system for power integrity characterization using one bias supply. The measurement system is operated by the bias voltage provided to logical blocks such as Core and IO block in a microprocessor since another supply power rail for the measurement system can create a coupling to the existed power rails. The power supply noise is repetitive since it is created by repetitive on chip circuit activities. The voltage range that can be measured by the system is ±25% of VCC; (including noise which exceeds the power supply voltage) and the range of the noise measurement frequency is up to 1.5GHz. The proposed measurement system is composed of two main sections; one is a sampling and detection system and the other is an effective ADC. In addition, the proposed system is designed in 90nm CMOS technology and is specified to be interacted with system support such as software for a trigger signal and JTAG.

In this paper, a low-voltage (sub-1 Volt) resistor-free voltage reference is presented. The complete design was simulated and laid out in AMI 0.5 μm CMOS process. The design provides a temperature coefficient of 12.8 ppm/ C over a temperature range from 25 to 100 °C and occupies an area of 0.037 mm . Circuit description and experimental results of the proposed design are also presented.

A new implementation of EVM measurement has been developed in a production test environment using an FPGA-based DSP processor within an ATE test solution. The focus of interest is in identifying key areas of the DSP that affect measurement quality and optimizing their execution on an FPGA to increase measurement accuracy, precision, repeatability, and reduce test time. This approach defines a real-time processing methodology for signal demodulation and EVM calculation as opposed to traditional PC-based post processing and offline computation of EVM. The analysis of the DSP elements and their corresponding error artifacts are presented in a standard approach to EVM measurement. The experimental results of the digital demodulation system and EVM measurement in MATLAB/Simulink are compared against a bench-top Rohde&Schwarz complex signal generator and vector signal analyzer to qualify the results.

A high-speed scalable programmable divide-by-N frequency divider is presented. The divider includes a new proposed state look-ahead parallel counter with a basic conventional D-type Flip-Flop (DFF) circuit. The counter is structured from two modules of 2-bit counter stages separated by DFF buffers, where all are triggered at the edge of the input clock. The reload circuit is a single DFF buffer, while the detecting count circuit is constructed from a two level decoder. The M-bit divider critical path delay, which is independent of technology, is approximated to [3.5 + Log4 (M)] of a unit delay close to a 2-input NAND gate. This results in a measured frequency, which slightly drops to about 6% against the increase of the divider bit size. Furthermore, the divider circuit is attractive for continued technology scaling since the architecture is based on using identical modules of small count of CMOS transistors with only threshold voltage technology limitations. The measure rate of the number of transistors is approximated to a linear increase of about 17% per a two-bit increase of the divider size. The presented 8-bit programmable divide-by-N frequency divider is capable of operating up to 2 GHz for a 1.35 V power supply voltage with a maximum power consumption of 16.78 mW and a maximum frequency divider factor of N=256 using the TSMC 0.15 mum digital CMOS process, and gives a measured area of 95*143 mum2with a total count of 508 transistors.

In this paper, an embedded jitter measurement system is presented. The system uses the Vernier delay method to achieve high resolution. The jitter test circuit is implemented using current-mode logic, so it is fast enough for testing today's high-speed I/O signals such as PCI Express. And the differential structure also makes the circuit immune to common-mode noise. Other advanced jitter measurement functions can be added to the time interval analyzer, (TIA) system presented here. Simulation results show that the TIA system can be used with low-cost ATEs to meet jitter measurement requirements

A low-power CAM design using a 12-transistor cell is proposed. The CAM cell is based on the conventional 6T cross- coupled inverters used for storing data with an addition of two NMOS transistors for reading out. In addition, the CAM has another four transistors for mask comparison operation through classical pre-charge operation. The read-out port exploits a pre- charge reading mechanism in order to alleviate the drawback of power consumption generated from sensing amplifiers and all other related synchronization circuits which are structured in every column in the memory. Thus, the read and match features can have concurrent operations. An experimental CAM structure of storage size 64-bit x 128-bit is designed using 0.18- μm CMOS single poly and three layers of metals measuring a cell die area of 24.4375 μm2and a total silicon area of 0.269192 mm2. The circuit works up to 200 MHz in simulation with total power consumption of 0.016 W at 1.8-V supply voltage

Mixed-mode s-parameters assist in the design and characterization of four-port and three-port differential RF/microwave circuits. A new method for extracting mixed-mode s-parameters for four-port and three-port circuits modeled with SPICE is presented in which the s-parameters are extracted from node voltages. This method is efficient for circuits that are designed in SPICE and is free from any assumptions or approximations. Furthermore, this method provides valuable information on the relationships between the extracted mixed-mode s-parameters and the circuit's operation. This method is verified for a differential transformer circuit.

In the nanometer design regime, analog and RF circuits are expected to be increasingly susceptible to process, noise and thermal variations. Shifting threshold voltages on the NMOS and PMOS devices of a mixer, LNA or power amplifier, for example, can affect the design specifications of such circuits (such as gain). Thermal variations can affect carrier mobilities of NMOS and PMOS devices differently, further affecting circuit performance. To solve these problems, a new self-calibration approach driven by a Specification-driven built-in self test procedure (S-BIST) is proposed. This S-BIST procedure uses alternate specification test techniques to predict the performance specifications of the circuit-under-test from the S-BIST response. The results of the S-BIST procedure are used to change the operating point of the circuit to maximally compensate the analog/RF circuit for loss of performance. The proposed S-BIST approach has been applied to a 2.4-GHz low noise amplifier and performs well in the presence of temperature and process variations.

In today's high-speed/high-density very large scale integrated (VLSI) circuit designs with coupled interconnect lines, signal transients are strongly correlated with the input switching patterns. Signal-delay variations due to the input-switching patterns may be more than /spl plusmn/50% of the delay of an isolated single line. Thus, blind static timing-analysis techniques without consideration of the detailed switching effects may not be accurate enough to meet tight timing margins for today's deep submicron (DSM)-based VLSI circuits. In this paper, the signal-transient responses of multicoupled interconnect lines due to various input-switching patterns are analyzed in terms of the effective capacitances and effective inductances. Thereby, the critical delay line of multicoupled interconnect lines is decoupled into an effective single-isolated line. With the proposed novel decoupling technique for multicoupled interconnect lines, the accurate dynamic delay of strongly coupled interconnect lines can be readily determined with physical layout information. For example, in switching patterns, the paper shows that the signal delays calculated by using the effective single-line models have excellent agreement with SPICE simulations using the generic coupled interconnect circuit models. That is, the accuracy for both RC-dominant lines and RLC lines is within 10% error (but often within 5% error). Thus, without any significant modification of existing IC computer-aided design frameworks, the technique can be directly as well as usefully employed for accurate timing verification of DSM-based VLSI designs.

Novel signal integrity verification models and algorithms for inductance-effect- prominent RLC interconnect lines are developed by using a traveling-wave-based waveform approximation (TWA) technique. The multicoupled line responses are decoupled into the eigenmodes of the system in order to exploit the TWA technique. Then, the response signals are mathematically represented by the linear combination of each eigenmode response based on TWA, followed by reporting the signal integrity models and algorithms for the multicoupled lines. The signal integrity of VLSI circuit interconnects is complicatedly correlated with input signal switching-patterns, layout geometry, and termination conditions. It is shown that the technique can be efficiently employed for complicated multicoupled interconnect lines with various termination conditions and the signal transients based on the technique have excellent agreement with SPICE simulations. Thus, with the proposed technique, the switching-dependent signal delay, crosstalk, ringing, and glitches of the inductance-effect-prominent RLC interconnect lines can be accurately as well as efficiently determined.

In the last three years, a program focused in mixed-signal/RF IC testing has been established at the University of Florida. Industry collaboration has been key in providing direction, support and equipment for this effort. Through this effort, I see a strong role for building RF IC test research groups in the university environment to better solve the hard IC test problems. In addition, the mixed-signal and RF IC test professors would greatly benefit industry by influencing the RF IC design curriculum at the university to include analog and RF DfT concepts.

Today's high-speed very large scale integration interconnects are becoming inductively dominated (moderate Q) resistance-inductance-capacitance (RLC) transmission lines. The time-domain system responses of RLC interconnect lines driving load capacitances cannot be accurately represented by using a finite number of poles with exception for a particular case of RC-time-constant-dominant (low Q) RLC systems. In this paper, a new traveling-wave-based waveform approximation technique is presented. The method suggests that a steady-state traveling wave is approximately determined by a three-pole approximation technique. Then the time-domain response of the system can be accurately determined by using the traveling waves that are modeled by multiple reflections. The signal delay models of the RLC interconnect lines are derived as a closed form. The technique is verified by varying the source resistance, load impedance, and transmission line circuit model parameters of several RLC lines. The results show excellent agreement with HSPICE simulation results. That is, approximately 5% error in a 50% delay calculation can be achieved.

As very large scale integration (VLSI) circuit speed rapidly increases, the inductive effects of interconnect lines strongly impact the signal integrity of a circuit. Since these inductive effects make the signal integrity problems much more serious as well as intricate, they become one of the critical issues in today's high-speed/high-density VLSI circuit design. In this paper, a generalized traveling-wave-based waveform approximation (TWA) technique is presented which can be accurately as well as efficiently employed for the signal integrity verification of the inductively dominated (moderate Q) multicoupled RLC transmission line system. The technique is composed of three steps. First, the signals in the multicoupled (n-coupled) transmission line system are decoupled into n-isolated eigen-modes (i.e., basis vectors). Next, the slow-transient low-frequency characteristics of the system response are determined, approximately, in the frequency-domain by using the dominant poles of the basis vectors. Finally, the fast-transient high-frequency characteristics of the system response are calculated in the time domain by using the traveling wave characteristics of the basis vectors. It is shown that the time-domain responses of the multicoupled RLC transmission line system can be accurately as well as efficiently modeled with the generalized TWA technique. Then, in inductance-dominant multicoupled interconnect networks, switching-dependent signal integrity, i.e., signal delay, crosstalk, ringing, and glitches are investigated extensively with the proposed technique.

A new fast and accurate capacitance determination methodology for intricate multilayer VLSI interconnects is presented. Since a multilayer interconnect structure is too complicated to be directly tractable, it is simplified by investigating charge distributions within the system. The quasi-three-dimensional (3-D) capacitances of the structure are then determined by combining a set of solid-ground-based two-dimensional (2-D) capacitances and shielding effects that can be independently calculated from the simplified structure. The shielding effects due to the neighboring lines of a line can be analytically determined from the given layout dimensions. The solid-ground-based 2-D capacitances can also be quickly computed from the simplified structure. Thus, the proposed capacitance determination methodology is much more cost-efficient than conventional 3-D-based methods. It is shown that the calculated quasi-3-D capacitances have excellent agreement with 3-D field-solver-based results within 5% error.

A five-terminal, charge-based model for the thin-film silicon-on-insulator (SOI) MOSFET is implemented in SPICE2, thereby enabling, for the first time, proper simulation and CAD of SOI MOS integrated circuits in which the unique floating-body and back-gate-bias effects can be significant. The implementation is achieved, without having to rewrite the circuit simulator, by developing a general method for incorporating new charge-based device models into SPICE2 that utilizes user-defined controlled sources (UDCS's). The utility and computing efficiency of the SOI MOSFET model implementation are demonstrated by simulating several representative SOI MOS circuits.