EDBT 2026 Demo / reviewers in the wild / expert
Mark Basel
dblp:36/5703
· DBLP profile ↗
3ranked-venue papers
0as first author
0since 2021 · last 2001
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2Applied, interdisciplinary, general and emerging computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Electronic design automation · 98% Interconnection networks and networks-on-chip · 2% |
Topics — the 8 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › physical design
parasitic extraction |
0.1 | 2 | 2001 | Parasitic extraction: current state of the art and future trends · Proc. IEEE 2001 Parasitic Extraction Accuracy - How Much is Enough? · DAC 1999 |
Electronic design automation › signal integrity
crosstalk analysis |
0.0 | 1 | 2001 | Parasitic extraction: current state of the art and future trends · Proc. IEEE 2001 |
Electronic design automation › interconnect modeling
interconnect parasitic modeling |
0.0 | 1 | 2001 | Parasitic extraction: current state of the art and future trends · Proc. IEEE 2001 |
Electronic design automation
signal integrity |
0.0 | 1 | 2001 | Parasitic extraction: current state of the art and future trends · Proc. IEEE 2001 |
Electronic design automation › circuit simulation
model order reduction |
0.0 | 1 | 2001 | Parasitic extraction: current state of the art and future trends · Proc. IEEE 2001 |
Electronic design automation
physical design |
0.0 | 1 | 1992 | Tools to Aid in Wiring Rule Generation for High Speed Interconnects · DAC 1992 |
Electronic design automation
interconnect modeling |
0.0 | 1 | 1999 | Parasitic Extraction Accuracy - How Much is Enough? · DAC 1999 |
Interconnection networks and networks-on-chip
high-speed interconnect |
0.0 | 1 | 1992 | Tools to Aid in Wiring Rule Generation for High Speed Interconnects · DAC 1992 |
Methods — techniques the papers use, named apart from their topics
inductance extraction · 0.0delay calculation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2001 | Parasitic extraction: current state of the art and future trendsabstractWith the increase in circuit performance (higher speeds) and density (smaller feature size) in deep submicrometer (DSM) designs, interconnect parasitic effects are increasingly becoming more important. This paper first surveys the state of the art in parasitic extraction for resistance, capacitance, and inductance. The paper then covers other related issues such as interconnect modeling, model order reduction, delay calculation, and signal integrity issues such as crosstalk. Some future trends on parasitic extraction, model reduction and interconnect modeling are discussed and a fairly complete list of references is given. William H. Kao, Chi-Yuan Lo, Mark Basel, Raminderpal Singh |
Proc. IEEE | 3 |
| 1999 | Parasitic Extraction Accuracy - How Much is Enough?abstractNo abstract available. Paul D. Franzon, Mark Basel, Aki Fujimara, Sharad Mehrotra, Ron Preston, Robin C. Sarma, Marty Walker |
DAC | 2 |
| 1992 | Tools to Aid in Wiring Rule Generation for High Speed Interconnects
Paul D. Franzon, Slobodan Simovich, Michael B. Steer, Mark Basel, Sharad Mehrotra, Tom Mills |
DAC | 4 |