Photoplethysmography (PPG) has emerged as a critical non-invasive technique for cardiovascular health monitoring through wearable devices, yet the physiological mechanisms underlying PPG signal formation are not completely understood. This affects the development of accurate diagnostic tools and personalized health monitoring systems. To overcome it, analysis of how cardiac output and other physiological factors are reflected in PPG, especially at the wrist, is required, and end-to-end PPG simulation methods have been developed for this purpose. However, these methods have limitations in either accuracy or computational efficiency. To address this gap, we present a comprehensive end-to-end framework for simulating wristbased PPG signals by integrating radial artery hemodynamics with optical light transport modeling through skin. In our approach, first, cardiac parameters are used to generate the cardiac output. This is passed into an upper left limb artery simulation, which produces arterial pressure, flow, and crosssectional area variation at each location. These waveforms at the radial artery are used by a novel, computationally efficient light transport simulation through the skin to generate the PPG signal. The morphological features of the PPG waveform generated by our method are closer to those of real PPG data compared to simulations that utilize a deterministic method as an alternative to light transport simulation. Furthermore, our light transport simulation method is significantly faster than the Monte Carlo method used for more accurate simulations. Therefore, our approach provides a balance of both computational efficiency and accuracy in wrist PPG simulation, aiding the development of personalized cardiovascular monitoring systems.

SMTPE ST 2110 is a professional video over IP standard which enables uncompressed video to be transported as separate video, audio and ancillary data streams, allowing true flexibility in media workflows. Uncompressed video transmission allows professional video environments to achieve high quality video distribution while meeting strict latency requirements. Although this standard can be implemented on software, hardware solutions can achieve superior performance, lower latency and lower power consumption while efficiently handling jitter and packet bursts. This paper presents an FPGA based hardware implementation of a SMPTE ST 2110 compliant end to end solution supporting uncompressed video resolutions of up to 4K at 30fps. Due to its scalability, the architecture can be easily extended to support higher video resolutions and/or multiple video streams. Additionally, the interface modularity of the architecture enables integration with any video interface type. In this work, a Serial Digital Interface (SDI) interface is used. The proposed architecture consists of a replicable video processing pipeline for each stream, a Session Description Protocol (SDP) compliant network configuration unit and a SMPTE ST 2059-1/2 compliant time synchronization unit common to all streams, with network access via a 10G UDP/IPv4/Ethernet stack. All modules other than the Ethernet core and SDI interface modules can operate at 200MHz even though 4K 30fps video processing can be achieved with a minimum operating frequency of 100MHz.

Due to the increasing heterogeneity in network user requirements, dynamically varying day to day network traffic patterns and delay in network service deployment, there is a huge demand for scalability and flexibility in modern networking infrastructure, which in return has paved way for the introduction of Software Defined Networking (SDN) in core networks. In this paper, we present an FPGA-based switch which is fully compliant with OpenFlow; the pioneering protocol for southbound interface of SDN. The switch architecture is completely implemented on hardware. The design consists of an OpenFlow Southbound agent which can process OpenFlow packets at a rate of 10Gbps. The architecture contains a primary pipeline which is capable of achieving core network throughputs and an auxiliary pipeline leading to the Openflow agent. Single clock cycle Content Accessible Memory (CAM) architecture supports the overall design to achieve its throughput and latency requirements. The proposed architecture speed scales up to 400Gbps while it consumes only 60% resources on a Xilinx Virtex-7 featuring XC7VX485T FPGA. Switch fabric is capable of connecting to a control plane running upon a host PC via PCIe which provides an opportunity at research level to explore SDN in core networks. Moreover, the architecture is experimented for different scaled versions using line rates of 10G, 25G and 100G. By using FPGA based embedded platforms which support sufficient number of ports and their line rates, this architecture can be deployed in core networks.

Convolutional Neural Networks (CNNs) are widely used in deep learning applications, e.g. visual systems, robotics etc. However, existing software solutions are not efficient. Therefore, many hardware accelerators have been proposed optimizing performance, power and resource utilization of the implementation. Amongst existing solutions, Field Programmable Gate Array (FPGA) based architecture provides better cost-energy-performance trade-offs as well as scalability and minimizing development time. In this paper, we present a model-independent reconfigurable co-processing architecture to accelerate CNNs. Our architecture consists of parallel Multiply and Accumulate (MAC) units with caching techniques and interconnection networks to exploit maximum data parallelism. In contrast to existing solutions, we introduce limited precision 32 bit Q-format fixed point quantization for arithmetic representations and operations. As a result, our architecture achieved significant reduction in resource utilization with competitive accuracy. Furthermore, we developed an assembly-type microinstructions to access the co-processing fabric to manage layer-wise parallelism, thereby making re-use of limited resources. Finally, we have tested our architecture up to 9×9 kernel size on Xilinx Virtex 7 FPGA, achieving a throughput of up to 226.2 GOp/S for 3×3 kernel size.

This paper presents a novel low-complexity VLSI architecture for an EEG Feature Extraction Platform for wearable health monitoring systems. It integrates a processing core unit, preprocessing FIR filter block and an FFT accelerator. The platform supports 8 scalp EEG channels and it can be scaled up to 16 or 32 EEG channels. In this paper, we analyze several architectural optimizations for hardware implementation of features such as Power Spectral Density, Discrete Wavelet Transform, Autoregression etc. The proposed architecture is easily scalable to new feature extractors. An FFT accelerator is proposed to improve the flexibility of the platform. We provide a comparison with software models for each feature extractor and also validate the platform by implementing a seizure detection algorithm on CHB-MIT Scalp EEG database with an accuracy of over 95%.

Screen content coding (SCC) extension to High Efficiency Video Coding (HEVC) offers substantial compression efficiency over the existing HEVC standard for computer generated content. However, this gain in compression efficiency is achieved at the expense of further computational complexity with several resource hungry coding tools. Hence, extension of SCC to HEVC hardware encoders can be challenging. This paper presents resource efficient hardware designs for two key SCC tools, Intra Block Copy and Palette Coding. Moreover, a new hash search approach is proposed for Intra Block Copy, while a hardware friendly palette indices coding scheme is suggested for Palette Coding. These designs are targeted to achieve the throughput necessary for an 1080p 30 frames/s encoder, and incurs coding loss of 11.4% and 5.1% respectively in all intra configurations. The designs are synthesized for a Virtex-7 VC707 evaluation platform.

Most of the intrusion detection and prevention systems (NIDS/NIPS) are utilizing signature based matching which makes use of a stored rule base for distinguishing malicious network traffic. Dynamic rule-base updates has become a requirement due to the increasingly large number of new attack types identified every day, while the downtime associated with rule base updates has become a major drawback in hardware based Network Intrusion Prevention Systems. In addition, the NIPS are facing the challenge of expanding their throughput to cope with the ever growing high bandwidth requirement. This paper presents a novel scalable architecture for a NIPS with stateful packet inspection. The implementation is capable of processing Snort signatures and also analyzing packet streams to detect attacks with TCP segment manipulation. The system ensures run-time rule reconfigurability, which eliminates the risk of downtime due to rule-base updates, providing high throughput with low latency. The architecture is capable of detecting and blocking malicious content passing through a computer network at a line rate of 10 Gbps, working at 200 MHz on a Xilinx VC707 Evaluation board.

Higher compression efficiency in HEVC encoders comes with increased computational complexity, making real time encoding of high resolution videos a challenging task. This challenge can be addressed by software, yet hardware solutions are more appealing due to their superior performance and low power consumption. This paper presents an FPGA based hardware implementation of an all intra HEVC encoder, which can encode 8 bits per sample, 1920×1080 resolution, 30 frames per second raw video, that is viable in real time even at low operating frequencies. A major obstacle to real time encoding in available architectures is the dependency created by reference generation. Moreover, each coding unit (CU) has to be processed in multiple configurations to determine the most efficient split and prediction mode representation, based on the bit stream generated. We propose a new three stage architecture to reduce these dependencies and increase parallelism. Feedback needed for CU split and prediction direction decision from binarization is avoided by a Hadamard based early decision method. Feedback constrained coefficient and reconstruction derivation module exploits several optimization techniques. All modules can operate at 200 MHz and the encoder can achieve real time encoding with a minimum operating frequency of 140 MHz. The design consumes 83K LUTs, 28K registers, and 34 DSPs when implemented on Xilinx Zynq ZC706.

With the popularization of a quad high-definition/4K video being dependent on the availability of real-time High Efficiency Video Coding (HEVC) decoders, hardware implementations have become more appealing due to their superior performance and low power consumption. In this paper, a field-programmable gate array (FPGA)-based hardware implementation of a 4K 30 frames/s real-time HEVC decoder is presented. An elastically pipelined decoder architecture is used to absorb variations in processing time and each pipeline stage is optimized to use available FPGA primitives. FPGA-specific challenges in managing critical path delays to achieve a target operating frequency of 150 MHz required many architectural novelties, such as exploitation of the sparsity of transformed coefficient matrix, single-cycle reference pixel processing in intra prediction, and flexible$8 \times 8$block ordering in deblocking filter/sample adaptive offset filter. A high-throughput latency-aware cache architecture was used to reduce the external dynamic RAM access bandwidth by 70%. This work is compliant with the HEVC main profile at level 5 of the HEVC standard and only consumes 126K lookup tables, 58K registers, and 335 18-kb block RAMs when implemented on Xilinx Zynq 7045.

The inverse transform function of the HEVC Decoder has grown greatly in complexity with the addition of larger transform sizes and recent works have focused on efficient architectures that can achieve the required throughput. In this work we make the observation that a majority of the coefficients in a typical transform operation is zero, and therefore has no impact on the final outcome. We propose an architecture that can efficiently operate on such sparse matrices and introduce a scheduling strategy which completes a 2D IDCT with bare minimum iterations, with the added advantage of being able to integrate seamlessly with the entropy decoder without a coefficient reordering buffer. Experiments show that although the performance of this approach is scalable with the bit rate, a 120 MHz operating frequency is sufficient to handle QHD @ 48 Mbps, which is less than one third of the frequency requirement of prior work.

The objectives of this research are to assess the impact of ICT on learning and teaching in secondary schools in Sri Lanka, to assess the current ICT usage in schools, and to derive a set of recommendations that would help future policy making. The research found that there is no direct relationship between the computer usage of students and their perceived impact of ICT on learning. Both studentspsila and teacherspsila attitude toward the usage of ICT for learning and teaching purposes are statistically-significant and positively-related to their perceived impact. However, the relationship between ICT skills and their perceived impact of ICT on learning was comparatively more significant for students than teachers and principals. Government interventions on training are not related to the perceived impact of ICT of teachers and principals. Furthermore, research found that the mere presence of ICT infrastructure in schools does not contribute towards the learning skills of students.

Multiple visual features can be used to track objects in environments where the use of a single visual feature is not sufficient. We have proposed an alternative method to feature integration by way of feature substitution where the dominant feature at any instant is used for tracking. The problem of increased computational cost resulting from the use of multiple features is addressed by using software optimization techniques. Here we use software threads and special instructions provided in MMX processors to increase the frame rate. Experimental results indicate that it is not always necessary to adopt a hardware based approach for real time object tracking even when the computational cost is high.