Demo Data from EDBT 2026 / reviewers in the wild / expert
Mukesh Puri
dblp:36/6285
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 2000
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
hardware verification and test |
0.0 | 1 | 2000 | Testing SRAM-Based Content Addressable Memories · IEEE Trans. Computers 2000 |
Electronic design automation › hardware verification and test
memory testing |
0.0 | 1 | 2000 | Testing SRAM-Based Content Addressable Memories · IEEE Trans. Computers 2000 |
Methods — techniques the papers use, named apart from their topics
march c algorithm · 0.0concurrent detection algorithm · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2000 | Detection of Inter-Port Faults in Multi-Port Static RAMsabstractThis paper deals with testing of inter-port faults in multi-port static random access memories (SRAMs). An inter-port fault is caused by a short between word/bit lines of different ports in a multi-port SRAM. By considering different implementations of the SRAM and its layout, an approach with achieves 100% coverage of fault detection, is proposed. The two-step approach is based on two novel algorithms: MMCA (Modified March C Algorithm) and WIPD (Write Inter-Port Detection). It is shown that inter-port fault detection is a combinatorial problem; hence, MMCA and WIPD must be executed a multiple number of times depending on the types, number of ports and line arrangement in the layout. Jun Zhao 0005, V. Swamy Irrinki, Mukesh Puri, Fabrizio Lombardi |
VTS | 3 |
| 2000 | Testing SRAM-Based Content Addressable MemoriesabstractThis paper presents an extensive model and algorithms for detecting faults in SRAM-based dual-port and uni-port CAMs (Content Addressable Memories). This model is based on analyzing the functionalities of a cell of an SRAM-based CAM and dividing it into two parts (storage and comparison parts). It is shown that faults can affect one or both parts. While storage faults can be detected using a traditional test algorithm (such as the March C), faults affecting the comparison part of the cell require a substantially different approach. A complete characterization of these faults is presented; by analyzing the structure of the cell in the dual and uni-port configurations, physical faults (such as stuck-at, stuck-open, stuck-on, bridge) in lines and transistors can be mapped to three functional fault sets by the execution of the comparison operation. Two new detection algorithms (directly compatible with the world-oriented March C algorithm, as widely used in existing commercial tools) are proposed; 100 percent coverage is achieved. The first algorithm (Concurrent Detection Algorithm or CDA) employs concurrent operations for testing a dual-port CAM; the second algorithm (Non Concurrent Detection Algorithm or NCDA) uses nonconcurrent operations and can be used for testing dual-port as well as uni-port CAMs. CDA requires eight passes and (10N+2L) tests, where N is the number of words of the CAM and L is the width of a word. NCDA requires eight passes, too, but (12N+2L) tests. The number of tests required by CDA (and NCDA, too) is significantly less than required by existing algorithms. Jun Zhao 0005, V. Swamy Irrinki, Mukesh Puri, Fabrizio Lombardi |
IEEE Trans. Computers | 3 |