The complexity of EEG data presents significant challenges for accurate diagnosis in neurological conditions such as Alzheimer’s disease. In this paper, we introduce Explainable Orthogonal Attention Networks, a novel approach for EEG-based analysis that decouples spatial and temporal features to more effectively capture disease-related neural patterns. By leveraging orthogonal attention mechanisms, our model independently processes spatial relationships across EEG channels and temporal dynamics, enhancing both explainability and predictive performance. Our approach outperforms baselines, achieving superior performance in objective metrics, with a 14% relative improvement, while offering insights into the neural mechanisms underlying Alzheimer’s disease. Using attention maps and spectral analysis, we identified critical parietal and frontal contributions, along with EEG markers like elevated theta and reduced alpha power, commonly associated with Alzheimer’s disease. This method represents a significant step forward in developing explainable and high-performing EEG-based diagnostic tools. We will make the code and model’s weights publicly available upon publication at anonymized.

This paper proposes an approach for reducing the phase error of PLL-based quadrature voltage-controlled oscillators (PLL-QVCOs). The method leverages the back-gate coupling technique to deliberately create a mismatch between the I and Q oscillators that, in effect, reduces or cancels out the effects of unwanted mismatches within the oscillator cores. This technique makes the design more power efficient with a low phase error and phase noise performances simultaneously. It increases the figure of merit (FoM) by 4.7 dB as compared to the conventional design. The proposed PLL-QVCO is designed in a 65-nm CMOS process consuming 5.35 mW from a 0.8 V supply and covers a frequency range of 5.2 to 6.15 GHz. Post-layout simulation results demonstrate phase noise and FoM of -126.1 dBc/Hz and 193.3 dB, respectively, at 1 MHz offset frequency.

In this work, we present an approach called third-derivative-based sampling (TDS), which is a non-uniform sampling technique that can be used in a variety of applications. Here, we will focus on applying the technique to electrocardiogram (ECG) signals. We also present a possible hardware implementation of the approach. The TDS method uses cubic spline interpolation for sampling the signal as well as signal reconstruction. As compared to other non-uniform sampling techniques, TDS offers an improved accuracy of the reconstructed signal and/or a reduction in the number of retained samples which enhances the compression factor (CF). Such improvements will also lead to an enhanced power efficiency in ECG monitoring systems. Users can control the associated reconstruction error by adjusting the maximum number of samples that can be disregarded (N) and/or the magnitude of the fourth derivative of the signal. The presented results demonstrate that the proposed method can offer up to 20% improvement in the CF as compared to the state-of-the-art techniques reported in the literature without compromising the reconstruction error. Alternatively, it can offer up to 53% enhancement in the accuracy of the reconstructed signal for a given CF. By integrating the proposed TDS block into an ECG data acquisition and processing system, the overall power consumption of the system can be reduced since only a small fraction of samples (proportional to CF) are kept and processed.

Varactors in RF CMOS processes often have significantly lower Q- factor ($Q_{VAR}$) than inductors and transformers at mm-wave frequencies. Direct connection of varactors to the outputs of an LC oscillator lowers overall tank Q,$Q_{T} < Q_{VAR}$, and at the same time, increases the ratio of parasitic capacitance to total tank capacitance which limits frequency tuning range (FTR). Instead, magnetically coupling a varactor to the oscillator core using an asymmetric transformer, where the core is connected to the primary and varactor to the secondary, limits the drop in$Q_{T}$. The ratio of parasitic capacitance to total tank capacitance is also reduced. The varactor can also be operated in accumulation-mode, with a larger$Q_{VAR}$. Thus, both FTR and phase noise (PN), in comparison to traditional tanks in LC VCOs, are improved simultaneously. In this paper, two VCO prototypes are implemented in 65-nm CMOS. A 60 GHz self-mixing VCO with a VCO core operating at 20 GHz shows an FTR of 18.5%, a PN of −92.5 dBc/Hz at 1 MHz offset, and an FoM$_{T}$of −187.1 dBc/Hz. A 25 GHz VCO shows an FTR of 29.9%, a PN of −107.9 dBc/Hz at 1 MHz offset, and an FoM$_{T}$of −194.2 dBc/Hz.

In this paper, a low-power crystal-less event-driven receiver that is suitable for biomedical implants is presented. The design is intended to be embedded into a smart stent, or can be used for other miniaturized biomedical implants as well as other size-constrained and low-power applications such as Internet of Things (IoT). In order to facilitate operation using harvested energy, the receiver operates from a low supply voltage of 0.5 V. The system uses an envelope detector with programmable scaling factor to provide a better trade-off between sensitivity and power consumption. A proof-of-concept receiver with two gain settings is designed and fabricated in a 0.13-μm CMOS process. The monolithic system does not require any external components, occupies a chip area of 0.208 mm2, and consumes 32 μW while achieving sensitivity of -50 and -53 dBm for the two different scaling factors.

This paper presents LC voltage-controlled oscillators (VCOs) that use integrated vertical-turn inductors (solenoids) in their tanks to alleviate frequency and phase pulling due to magnetic coupling when multiple VCOs are densely integrated. The vertical-turn inductor is symmetric, compact size and less susceptible to the substrate loss due to eddy currents, while its magnetic field is perpendicular to that of a conventional planar spiral inductor that is implemented on the same die. As a proof of concept, two free-running 40-GHz VCOs with low clock jitter using the proposed inductor are designed and laid out in a 65-nm CMOS technology. Based on electromagnetic (EM) simulation results, the proposed solenoid structure provides up to 30 dB more inductor-to-inductor isolation as compared to planar inductor structures at the desired frequency. The VCOs achieve a phase noise of -113 dBc/Hz at 10-MHz offset frequency, and draw 10.3 mA from a 1-V supply, resulting in a figure of merit (FOM) of -175 dBc/Hz. The circuit excluding pads occupies an area of 0.0324 mm2.

In this paper, we propose a technique to extend the tuning range (TR) of Colpitts complementary metal-oxide semiconductor (CMOS) voltage-controlled oscillators (VCOs). To achieve a wide tuning range, we use variable capacitive feedback to extend the tuning range while achieving lower phase noise (PN) than that of the conventional Colpitts VCOs. In addition, the structure benefits from the dynamic forward-body self-biased technique to reduce the power consumption and facilitate the start-up condition. As a proof-of-concept, a 28-GHz Colpitts oscillator, which is suitable for 5G wireless applications, is designed and laid out in a 65-nm CMOS process. Post-layout simulations in conjunction with electromagnetic (EM) simulations confirm the improved performance of the proposed technique. Based on the simulation results, the VC O achieves a PN of -115.7 dBc/Hz at 10-MHz offset, and TR of ~34.5% resulting in a figure of merit incorporating the tuning range (FOMt) of -189 dBc/Hz. The circuit consumes 4.3 mW from a 1-V supply and excluding the pads occupies a 0.12 mm2of silicon area.

In this work, we present a 0.13-um CMOS rectifier that is designed for wirelessly powered implantable devices in general, and for a wirelessly powered medical stent interface, in particular. A double-tuned transformer-based tunable matching network is co-designed with the differential cross-coupled rectifier at 910 to 970 MHz. The circuit model of the medical stent is also characterized for co-simulation with the circuit blocks. Post-layout simulation results show that for a -2.2 dBm available power received by the stent (which dually acts as an antenna in the context of smart stent applications), a rectifier power conversion efficiency (PCE) of 44% can be achieved for a 2 kΩ load. In this condition and with a 60 mV available voltage induced at the stent terminal from 910 to 970 MHz, a DC output voltage that is greater than 500 mV can be generated at the output of the rectifier.

Pixel-wise coded exposure, as an emerging field of research in computational imaging, is widely implemented in applications such as high-speed imaging, compressive sensing, and focal-stack imaging. In this paper, a complementary metal-oxide-semiconductor (CMOS) pixel design for binary coded exposure is presented. Based on an always-on charge distribution structure, the proposed pixel achieves programmable charge selection. A prototype image sensor chip, fabricated in a 0.13-μm CMOS process demonstrates pixel's capability of binary exposure encoding in 60 fps while operating from a 3.3 V supply.

Applications of the capacitive-micromachined ultrasonic transducers (CMUTs) operating in their fundamental frequency of vibration have been extensively studied. Recent research on asymmetric mode of vibration has shown promising results in construction of super resolution ultrasound images. This paper presents the design of a receiver circuit that supports both the fundamental and asymmetric modes of operation. The receiver includes transimpedance amplifiers that convert the current signals from the CMUT devices into voltage. Furthermore, low-power variable-gain stages are included to amplify the resulting signals and facilitate interfacing to the ultrasound imaging machine for additional processing and display. The receiver is designed and laid out in a 0.35-μm CMOS process. Post-layout simulations show that each receiver channel has a nominal gain of 110 dBΩ up to 10 MHz while consuming 925 μW from a 3.3 V supply.

Efficiency enhancement techniques for CMOS rectifiers used in wireless power harvesting applications such as radio-frequency identification (RFID) or biomedical implants are overviewed. More specifically, three recently proposed efficiency enhancement techniques, namely, switched-capacitor gate-boosting scheme, auxiliary cell scheme and quasi-floating-gate biased scheme are presented in which based on the RF input level, the gate-drive voltage of switching transistors in the differential-drive rectifier architecture is enhanced. The proposed designs are laid out in standard 0.13-μm CMOS and their performance metrics are compared with the state-of-the-art differential structures. Through dynamically adjusting the input capacitance of the rectifier, a dual-band input matching scheme is presented which enables efficient power delivery at two distinct frequencies.

In this paper, an ultra-low-power system for wireless monitoring of inductively coupled biomedical implants is presented. The system is fully integrated and composed of custom rectifier, alignment and monitoring circuits with enhanced performance. The proposed system is described in the context of a smart-stent system that monitors the re-narrowing of blood vessels at the smart-stent site. The building blocks of the system are designed and simulated in a 0.13-μm CMOS technology. Simulation results for the monitoring system show that the proposed rectifier provides 53% power conversion efficiency (PCE) for -10.36 dBm input power (in the alignment mode) and 62% PCE for -4.06 dBm input power (in the monitoring mode). The alignment unit is capable of operating by drawing a 12 μA from a supply voltage as low as 0.6 V and the monitoring circuit consumes as low as 176 μW.

This paper describes a fully differential low-noise switched-capacitor (SC) readout circuit that is intended for MEMS capacitive inertial sensors. The circuit uses a variation of correlated level shifting (CLS) technique to reduce the opamp finite gain error as well as to minimize the effects of opamp offset and low-frequency noise. The readout circuit is designed and laid out in a 0.8 μm CMOS process. For the purpose of simulations, the MEMS capacitive sensor is emulated by a pair of differential variable capacitors in Verilog-A. Post-layout simulation results demonstrate that the circuit achieves a capacitance noise floor of ~0.25 aF/√Hz at 500 Hz with a sensitivity of 12.42 mV/fF. The circuit consumes 555 μW from a single 5 V supply.

This paper presents a low-power 10-bit 50-MS/s successive approximation register (SAR) analog-to-digital converter (ADC). To reduce power and area, the monotonic switching procedure is combined with a parasitic-compensated split-capacitor DAC that also has an improved capacitor matching. The nonlinearity of the conventional split-capacitor DAC due to parasitic capacitance and capacitor mismatch is improved by modifying the capacitor bank so that the bridge capacitor is an integer multiple of the unit capacitor (as opposed to fractional multiple in the conventional circuit) and by including two dummy unit capacitors connected to ground. The proposed 10-bit ADC is designed and simulated using a 90-nm CMOS technology. Post-layout simulation results show that at 1.0-V supply and 50 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 60.10 dB and consumes 0.32 mW with an input capacitance of 0.48 pF, resulting in a figure of merit (FoM) of 8.44 fJ/conversion-step. The ADC core occupies an active area of 215 × 215 µm2

This paper presents a 25 Gb/s clock and data recovery circuit using a full-rate clock and quadrature data phases. An adaptive slicer is used in the system front-end to equalize the distorted data to minimize duty-cycle distortion due to inter-symbol interference. The proposed structure uses an open-loop phase averaging block in the data path to generate the required quadrature phases for phase detection using a mixer. A receiver chip that uses an external clock and is based on the proposed technique is designed and laid out in a 90-nm CMOS process. The chip occupies 0.846 mm2and based on post-layout simulation results, it consumes 107 mW from a 1.2 V supply.

In this paper, a hybrid phase and frequency detector (PFD) for phase-locked loop (PLL) based clock and data recovery (CDR) applications is presented. The PFD starts the phase detection process in a binary mode, for a faster acquisition time and a higher pull in range, and after the binary PLL locks, the PD switches to the linear mode of operation resulting in a lower output jitter. The frequency acquisition range of the presented PFD is significant and it virtually can handle any data frequency. The data frequency can however be as high as the clock frequency. In all simulations of the PLL, the pull-in range of the PLL is limited by the tuning range of the voltage-controlled oscillator (VCO). A prototype PLL is designed in a 0.13 µm CMOS technology and has a lock range from 8.3 to 9.6 GHz, peak-to-peak jitter of 0.1 UI, and a worst-case lock time of 30 ns. The PLL consumes 36 mW from a 1.2 V supply.

An ultra-low-power area-efficient 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) is presented. To achieve ultra-low-power performance a DAC architecture is proposed that employs two rail-to-rail low-power unity-gain buffers and only 4 minimum-size capacitors instead of the conventional binary-weighted capacitor array. Thereby, power consumption and area are drastically reduced by virtue of lower switching activity and smaller size capacitor array. The proposed 8-bit SAR ADC is designed and simulated in a 0.13μm CMOS process. Simulation results show that for a 2.4 kHz (12.4 kHz) input signal while sampling at 25 kHz, the ADC achieves an ENOB of 7.9 (7.8), consumes 290 nW (350 nW) form a 0.8 V analog supply and a 0.6 V digital supply, and achieves a FoM of 48 fj/conversion-step (62 fj/conversion-step).

Push-push voltage-controlled oscillators (VCOs) achieve high oscillation frequencies by relying on the boosted second harmonic component of the oscillator. These VCOs however, typically require a high power to deliver a reasonable output swing. In this paper, we first derive an analytical expression that relates the amplitude of the second harmonic of an LC VCO to the C-V characteristics of its varactor. Then based on the results of the analysis, we present the design of a low- power and compact 27-GHz push-push VCO in 65 nm CMOS that exhibits a 28.5% tuning range while consuming 21 mW (including buffers) from a 1 V supply. At 27-GHz output, the VCO achieves a phase noise of -101 dBc/Hz at 1-MHz offset.

This paper presents a DSP-based SerDes reα that utilizes a hybrid speculative/successive-approxims register (SAR) analog-to-digital converter (ADC) to digitize data at the receiver's analog front-end. The proposed digitize technique addresses the high-power drawback of conventi flash-based ADCs used in sampling-based wireline recei' while allowing for digital equalization and data recover; 10 Gb/s through five time-interleaved channels. The receiver is designed and laid out in a 65 nm CMOS process. The occupies 1.53 mm2, and based on simulation results, it consu 263 mW from a 1 V core supply.

A programmable-gain amplifier (PGA) for in- vehicle power-line communication (PLC) is implemented in 0.13-μm CMOS. The PGA robustly operates over the extended automotive temperature range of -55°C to +125°C. A transconductance boosting technique is employed to improve the linearity of the amplifier. Post-layout simulation results confirm that the amplifier achieves a gain range of 0 to 60 dB, while the variation of each gain setting is less than 0.3 dB when the temperature changes from -30°C to +80°C, and is less than 0.9 dB when the temperature changes from -55°C to +125°C. The P1dBof the PGA at its minimum gain is 2.5 dBm, and the -3-dB bandwidth of the circuit at its maximum gain is 90 MHz. The PGA consumes less than 9.0 mW from a 1.2 V supply.

In this paper, an RF power harvesting system with automatic input tuning for long-range RFID tags is described. The system uses a high quality factor LC-matching network to boost the voltage of the received RF signal. Then a new high-efficiency voltage rectifier is used to extract DC voltage from the signal. In order to maximize the voltage gain of the matching circuit, a tuning loop automatically adjusts the center frequency of the input matching network to achieve the optimum output DC voltage. The loop uses a low-power up/down counter. The power of the counter is optimized by minimizing the number of unnecessary internal transitions. A proof-of-concept system is designed and simulated in a 0.13μm CMOS. It achieves an efficiency of 50% which compares favourably with that of current state-of-the-art RF power harvesting systems.

This paper examines a new architecture that combines super regeneration and time-based signal processing concepts to implement frequency-to-time conversion. The proposed structure can also be used to perform LC-tank oscillators testing by using simple and low-resolution digital circuits. Its front-end consists of two cross-coupled oscillators, triggered in time by two step-like signals with a time separation that is externally controlled. The time separation, together with the cross coupling arrangement, results in a controlled start-up time of oscillation from which the frequency of oscillation can be deduced. The start-up time, extracted using envelope detection and coarse time digitization circuits, is then non-destructively measured. A proof-of-concept circuit is designed and laid out in a standard 90-nm CMOS process. Post-layout simulations confirm the feasibility of the proposed approach.

This paper presents a differential low-noise high-resolution switched-capacitor readout circuit that is intended for capacitive sensors. Amplitude modulation/demodulation and correlated double sampling are used to minimize the adverse effects of the amplifier offset and flicker (1/f) noise and improve the sensitivity of the readout circuit. In order to simulate the response of the readout circuit, a Verilog-A model is used to model the variable sense capacitor. The interface circuit is designed and laid out in a 0.8 μm CMOS process. Post-layout simulation results show that the readout interface is able to linearly resolve sense capacitance variation from 2.8 aF to 0.3 fF with a sensitivity of 7.88 mV/aF from a single 5V supply (the capacitance-to-voltage conversion is approximately linear for capacitance changes from 0.3 fF to ~1.2 fF). The power consumption of the circuit is 9.38 mW.

An active inductor termination for high-speed I/O circuits is presented. In comparison with the conventional active-inductor-based circuits, the proposed topology operates from a lower supply voltage and/or consumes less power. A prototype of the active termination with a CML output driver is designed, simulated, and laid out in a 90 nm CMOS process. The eye-opening and jitter performance in the eye-diagram simulations of the active termination compare favorably with its passive counterparts. In comparison with a passive-inductor-based design, the circuit consumes additional 1.327 mW DC power while occupying a die area of 17 μm × 25 μm, which is more than 60 times smaller than the area of a termination circuit with a 0.8 nH passive inductor.

The design and simulation of a pair of bulk-driven low-voltage down-conversion mixers with on-chip transformer baluns is presented. The addition of a passive balun improves gain and can provide impedance matching for optional off-chip image-reject filters. The mixers operate in the 5.8 GHz ISM band and consume 1 mW while achieving an input-referred 1 dB compression point of 1 dBm with a gain of 3 dB and a noise figure of 27 dB, and a -13 dBm compression point with a gain of 13 dB and a noise figure of 17 dB.

Each new semiconductor technology node brings smaller transistors and wires. Although this makes transistors faster, wires get slower. As FPGA device designers strive to obtain the lowest possible circuit delays from a given technology node, they must take an increasingly interconnect-focused viewpoint in the design process. In particular, for long interconnect wires, signals now require rebuffering somewhere in the middle of the wire. This paper presents a framework for designing and evaluating long, buffered interconnect wires in FPGAs with near-optimal delay performance. Given a target physical wire length, width and spacing, the method determines the number, size, and position of buffers required to obtain the fastest signal velocity for programmable interconnect. A metric introduced during the design is the "path delay profile", or the arrival time of a signal at different points of a long wire. This method is used to design buffering strategies for interconnect based on 0.5mm, 2mm, and 3mm wire lengths in 180nm technology. These interconnect designs are coded into VPR along with an improved timing analyzer which accurately determines the "path delay profile" arrival times. Using VPR, average critical-path delay is reduced by 19% for 0.5mm wires and by up to 46% for 3mm wires over previous designs given in Lemieux et al. (2004)

An active inductor based bandpass radio-frequency (RF) filter circuit topology is presented that achieves a wide tuning range. Based on the proposed structure, a prototype 2th-order filter is designed, simulated, and laid out in a 0.18mum CMOS process. The center frequency of the filter can be tuned from 880MHz to 3.72GHz. The quality factor of the filter can also be tuned. The filter, including the input and output buffers, consumes between 12 to 26mW from a 1.8V supply and occupies a chip area of 115mum times 70mum

Recently, a new noncoherent sequence detection receiver for Bluetooth systems has been developed. The receiver is based on Rimoldi's decomposition of the Bluetooth transmit signal and its power efficiency was shown by software simulations. In this paper, a hardware implementation of the decoder for this receiver is presented. In particular, we describe a low-complexity Viterbi decoder that performs noncoherent sequence detection in a two-state trellis using per-survivor processing. The prototype decoder is implemented in a field programmable gate array (FPGA). The bit-error-rate performance of the implemented decoder is compared with that of the reference software simulations.

The effectiveness of passive guard-rings in high-frequency applications is studied using a simple approach. The results of this study reveal that while the performance of p+ guard-rings deteriorate as the frequency of operation increases, the n-well guard rings may exhibit the opposite trend. Furthermore, these results predict that n-well guard-rings can even act as p+guard-rings at very high frequencies. The effect of other guard-ring parameters, such as placement and shape, on its noise suppression capability is also investigated

Recently, there has been renewed interest in structured logic arrays due to a number of inherent advantages. However, before they will be more widely adopted, structured logic arrays must be able to compete with standard ASIC designs. This paper proposes a CMOS PLA based on a dynamic NOR architecture that uses an input-isolation technique along with a latch-based sense amplifier to achieve both high operating speed and low-energy consumption. The proposed architecture is designed and simulated in a 0.18mum CMOS technology. It improves the delay by 10% compared with the fastest reported PLA. It also achieves the lowest power-delay product of all other reported dynamic PLAs

Over the past ten years, as integrated circuits became increasingly more complex and expensive, the industry began to embrace new design and reuse methodologies that are collectively referred to as system-on-chip (SoC) design. In this paper, we focus on the reuse and integration issues encountered in this paradigm shift. The reusable components, called intellectual property (IP) blocks or cores, are typically synthesizable register-transfer level (RTL) designs (often called soft cores) or layout level designs (often called hard cores). The concept of reuse can be carried out at the block, platform, or chip levels, and involves making the IP sufficiently general, configurable, or programmable, for use in a wide range of applications. The IP integration issues include connecting the computational units to the communication medium, which is moving from ad hoc bus-based approaches toward structured network-on-chip (NoC) architectures. Design-for-test methodologies are also described, along with verification issues that must be addressed when integrating reusable components.

A decision-directed carrier-recovery technique for coherent demodulation of quadrature amplitude modulated (QAM) signals is proposed. This system adaptively tracks both the carrier frequency and phase of the received QAM signal's modulated carrier. The acquisition time of the proposed system is shown to be faster than that of conventional carrier-recovery schemes, especially when the initial carrier-frequency offset is relatively large, i.e. beyond a small fraction of the symbol rate. Also, the proposed method has a wider acquisition range compared to conventional techniques.