This paper describes the design and analysis of the 3.2 Gbps XDRtrade memory system of the Cell Broadband Enginetrade (Cell BE) processor developed by Sony Corporation, Sony Computer Entertainment, Toshiba and IBM. A system co-design and co-analysis approach was applied where different components of the system are designed and analyzed simultaneously to allow trade-offs to be made to optimize system electrical characteristics at low overall system cost. The XDR memory interface circuit implemented in the Cell BE processor, the power delivery system design and analysis, and the interface statistical signal integrity analysis will be described to illustrate this design and analysis approach.

This paper presents a neural network approach of pole clustering techniques to construct compact models of high-order systems. The approach can be used to reduce the order of complex models of high-speed interconnect systems obtained from standard rational approximation. The reduction of the order and complexity of circuit models are essential to improve the efficiency and stability of the time-domain simulation in very large distributed systems. The proposed procedure uses the clustering capabilities of self-organizing maps of artificial neural networks. Self-clustering maps are very suitable to identify the pole distributions, and efficiently generate cluster centers and representative poles for the compact models. To illustrate the validity of the method, examples of frequency-domain simulation results of high-speed memory system are given

In designing robust high-speed interconnect systems, the effects of parameter variations on system performance must be studied using statistical analyses. These analyses require repetitive circuit simulations to account for the randomness in parameter values caused by manufacturing and environmental changes. An accurate modeling technique is also essential for capturing the nonlinear relationships between channel parameters and performance. In this paper, the application of artificial neural networks to accurately capture the nonlinear mappings between parameters and performance to speed up the analysis of high-speed interconnect systems is described. An efficient set of data that uses a few simulations or experiments based on orthogonal arrays is proposed to train the neural network. The neural network can then serve to accurately and efficiently generate performance distributions. The usefulness and accuracy of the proposed approach is verified using an extreme data rate memory system that operates at a data rate of 3.2 Gb/s. The histograms and descriptive statistics of the eye height and timing jitter are compared with those obtained from traditional Monte Carlo, regression model, and worst case analyses

As the operating frequency of digital systems increases and voltage swing decreases, it becomes very important to characterize and analyze power distribution networks (PDNs) accurately. This paper presents the modeling, simulation, and characterization of the PDN in a high-speed printed circuit board (PCB) designed for chip-to-chip communication at a data rate of 3.2 Gbps. The test board consists of transmitter and receiver chips wirebonded onto plastic ball grid array (PGBA) packages on a PCB. In this paper, a hybrid method has been applied for analysis, which consists of the transmission matrix method (TMM) in the frequency domain and macromodeling method in the time domain. As an initial step, power/ground planes have been modeled using TMM. Then, the macromodel of the power/ground planes has been generated at the desired ports using macromodeling. Finally, the macromodel of the planes, transmission lines, and nonlinear drivers have been simulated in standard SPICE-based circuit simulators for computing power supply noise. In addition to noise computation, the self and transfer impedances of power/ground planes have been computed and the effect of decoupling capacitors on power supply noise has been analyzed. The methods discussed have been validated using hardware measurements.

An efficient transient analysis of diode switching circuits using the asymptotic waveform evaluation (AWE) technique is presented. The method accurately simulates the excess carrier redistribution phenomenon in a diode junction using a reduced order model. The diode model is derived by directly solving the carrier continuity equations in an analogous manner to that of the AWE solution to transmission-line equations. The method efficiently calculates the poles and the residues of the diode model by recursively generating the moments of the carrier concentrations. It reduces the computational cost by an order of magnitude over that for Linvill's multisection model of ladder or lattice networks of many lumped elements used to model carrier diffusion and the recombination process. The pole-residue model is capable of providing an increasingly accurate approximation to the characteristics of a diode under all operating conditions. The diode recovery phenomenon is simulated for illustration, and the improved accuracy is verified by comparisons with results from conventional methods and published works.