Due to technology scaling, integrated circuit manufacturing techniques are producing structures with large variabilities in their dimensions. To guarantee high yield, the manufactured structures must have the proper electrical characteristics despite such geometrical variations. For a designer, this means extracting the electrical characteristics of a whole family of structure realizations in order to guarantee that they all satisfy the required electrical characteristics. Sensitivity extraction provides an efficient algorithm to extract all realizations concurrently. This paper presents a complete framework for efficient resistance sensitivity extraction. The framework is based on both the Finite Element Method (FEM) for resistance extraction and the adjoint method for sensitivity analysis. FEM enables the calculation of resistances of interconnects of arbitrary shapes, while the adjoint method enables sensitivity calculation in a computational complexity that is independent of the number of varying parameters. The accuracy and efficiency of the algorithm are demonstrated on a variety of complex examples.

IBM's high-performance microprocessor designs leverage internally developed electronic design automation tools to create high-frequency, power efficient, and robust microprocessors. This paper describes some of the tools employed in the custom circuit design methodology in IBM. The tools described include a transistor-level block-based static timer, a static noise analysis methodology, and a transistor width tuner that optimizes performance and area. We also describe the application of electrical rule checking used to enforce consistent design practices. Finally, we discuss a macro extraction tool that determines parasitic resistance and capacitance of interconnect from a layout.