A concurrent error detectable adder with easy testability is proposed. The proposed adder is based on a multi-block carry select adder. Any erroneous output of the adder caused by a fault modeled as a single stuck-at fault can be detected by comparing the predicted parity of the sum with the parity of the sum, i.e., the XORed value of the sum bits, and comparing the duplicated carry outputs. The adder is also testable with only 10 input patterns under single stuck-at fault model. This property eases detection of a fault before the occurrence of a second fault. Both the concurrent error detectability to detect erroneous results and the easy testability to find a fault during operation are important for realizing reliable systems. Both the concurrent error detectability and the easy testability of the proposed adder are proven. A 32-bit adder has been designed. Its hardware overhead is about 70 percent. Its concurrent error detectability and 100 percent test coverage through the 10 patterns has been confirmed by fault simulation.

Level-testability of multi-operand adders consisting of carry save adders is shown by showing test design for them. A multi-operand adder is a main part of a multiplier. 6L+2 patterns are sufficient to test a multi-operand adder under cell fault model, where L denotes the depth of the multi-operand adder. A test method of the multi-operand adder used as a partial product compressor in a multiplier is also shown. This result gives an upper bound of the number of required test patterns for a multi-operand adder in any multiplier.