Demo Data from EDBT 2026 / reviewers in the wild / expert
Aparna Kotha
dblp:36/9033
· DBLP profile ↗
9ranked-venue papers
3as first author
0since 2021 · last 2016
0000-0002-8536-1627ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 2 first-authorSoftware engineering, systems software and programming languages · 4 · 1 first-authorSecurity and privacy · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
5 papers |
Program analysis · 57% Compilers and program optimization · 40% Debugging and program repair · 2% | |
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Parallel and multicore computing · 92% Embedded and real-time systems · 8% | |
| Network and information security
1 paper |
Systems and software security · 100% |
Topics — the 14 heaviest of 15, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Program analysis
static analysis |
0.4 | 2 | 2016 | A Stack Memory Abstraction and Symbolic Analysis Framework for Executables · ACM Trans. Softw. Eng. Methodol. 2016 Scalable variable and data type detection in a binary rewriter · PLDI 2013 |
Program analysis
symbolic execution |
0.4 | 2 | 2016 | A Stack Memory Abstraction and Symbolic Analysis Framework for Executables · ACM Trans. Softw. Eng. Methodol. 2016 A compiler-level intermediate representation based binary analysis and rewriting system · EuroSys 2013 |
Compilers and program optimization
binary rewriting |
0.4 | 3 | 2013 | Scalable variable and data type detection in a binary rewriter · PLDI 2013 A compiler-level intermediate representation based binary analysis and rewriting system · EuroSys 2013 Automatic Parallelization in a Binary Rewriter · MICRO 2010 |
Compilers and program optimization
intermediate representation |
0.3 | 2 | 2013 | Scalable variable and data type detection in a binary rewriter · PLDI 2013 A compiler-level intermediate representation based binary analysis and rewriting system · EuroSys 2013 |
Parallel and multicore computing › parallel programming models
automatic parallelization |
0.3 | 2 | 2015 | Affine Parallelization Using Dependence and Cache Analysis in a Binary Rewriter · IEEE Trans. Parallel Distributed Syst. 2015 Automatic Parallelization in a Binary Rewriter · MICRO 2010 |
Program analysis › data flow analysis
demand-driven analysis |
0.2 | 1 | 2016 | A Stack Memory Abstraction and Symbolic Analysis Framework for Executables · ACM Trans. Softw. Eng. Methodol. 2016 |
Compilers and program optimization
dependence analysis |
0.2 | 1 | 2015 | Affine Parallelization Using Dependence and Cache Analysis in a Binary Rewriter · IEEE Trans. Parallel Distributed Syst. 2015 |
Program analysis
binary analysis |
0.2 | 2 | 2013 | A compiler-level intermediate representation based binary analysis and rewriting system · EuroSys 2013 Scalable variable and data type detection in a binary rewriter · PLDI 2013 |
Parallel and multicore computing › parallel scheduling
malleable task scheduling |
0.2 | 1 | 2013 | Efficient multiprogramming for multicores with SCAF · MICRO 2013 |
Parallel and multicore computing › parallel scheduling
runtime scheduling |
0.2 | 1 | 2013 | Efficient multiprogramming for multicores with SCAF · MICRO 2013 |
Systems and software security › vulnerability analysis
information-flow vulnerability detection |
0.1 | 1 | 2016 | A Stack Memory Abstraction and Symbolic Analysis Framework for Executables · ACM Trans. Softw. Eng. Methodol. 2016 |
Systems and software security
vulnerability discovery |
0.1 | 1 | 2016 | A Stack Memory Abstraction and Symbolic Analysis Framework for Executables · ACM Trans. Softw. Eng. Methodol. 2016 |
Embedded and real-time systems › worst-case execution time analysis
cache analysis |
0.1 | 1 | 2015 | Affine Parallelization Using Dependence and Cache Analysis in a Binary Rewriter · IEEE Trans. Parallel Distributed Syst. 2015 |
Parallel and multicore computing › parallel programming models › directive-based programming
OpenMP |
0.0 | 1 | 2013 | Efficient multiprogramming for multicores with SCAF · MICRO 2013 |
Methods — techniques the papers use, named apart from their topics
symbolic execution · 0.5abstract interpretation · 0.5dependence analysis · 0.4cache analysis · 0.4static analysis · 0.3loop parallelization · 0.2binary rewriting · 0.2type inference · 0.2prototype recovery · 0.2feedback-based allocation · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2016 | A Stack Memory Abstraction and Symbolic Analysis Framework for ExecutablesabstractThis article makes three contributions regarding reverse-engineering of executables. First, techniques are presented for recovering a precise and correct stack-memory model in executables while addressing executable-specific challenges such as indirect control transfers. Next, the enhanced memory model is employed to define a novel symbolic analysis framework for executables that can perform the same types of program analyses as source-level tools. Third, a demand-driven framework is presented to enhance the scalability of the symbolic analysis framework. Existing symbolic analysis frameworks for executables fail to simultaneously maintain the properties of correct representation, a precise stack-memory model, and scalability. Furthermore, they ignore memory-allocated variables when defining symbolic analysis mechanisms. Our methods do not use symbolic, relocation or debug information, which are usually absent in deployed binaries. We describe our framework, highlighting the novel intellectual contributions of our approach and demonstrating its efficacy and robustness. Our techniques improve the precision of existing stack-memory models by 25%, enhance scalability of our basic symbolic analysis mechanism by 10×, and successfully uncovers five previously undiscovered information-flow vulnerabilities in several widely used programs. Kapil Anand, Khaled Elwazeer, Aparna Kotha, Matthew Smithson, Rajeev Barua, Angelos D. Keromytis |
ACM Trans. Softw. Eng. Methodol. | 3 |
| 2015 | Affine Parallelization Using Dependence and Cache Analysis in a Binary RewriterabstractToday, nearly all general-purpose computers are parallel, but nearly all software running on them is serial. Bridging this disconnect by manually rewriting source code in parallel is prohibitively expensive. Hence, automatic parallelization is an attractive alternative. We present a method to perform automatic parallelization in a binary rewriter. The input to the binary rewriter is the serial binary executable program and the output is a parallel binary executable. The advantages of parallelization in a binary rewriter versus a compiler include: (i) applicability to legacy binaries whose source is not available; (ii) applicability to library code that is often distributed only as binary; (iii) usability by end-user of the software; and (iv) applicability to assembly-language programs. Adapting existing parallelizing compiler methods that work on source code to binaries is a significant challenge. This is primarily because symbolic and array index information used by existing parallelizing compilers to take parallelizing decisions is not available from a binary. We show how to adapt existing parallelization methods to binaries without using symbolic and array index information to achieve equivalent source parallelization from binaries. Results using our x86 binary rewriter called SecondWrite are presented in detail for the dense-matrix and regular Polybench benchmark suite. For these, the average speedup from our method for binaries is 27.95X versus 28.22X from source on 24 threads, compared to the input serial binary. Super-linear speedups are possible due to cache optimizations. In addition our results show that our method is robust and has correctly parallelized much larger binaries from the SPEC 2006 and OMP 2001 benchmark suites, totaling over 2 million source lines of code (SLOC). Good speedups result on the subset of those benchmarks that have affine parallelism in them; this subset exceeds 100,000 SLOC. This robustness is unusual even for the latest leading source parallelizers, many of which are famously fragile. Aparna Kotha, Kapil Anand, Timothy Creech, Khaled Elwazeer, Matthew Smithson, Greeshma Yellareddy, Rajeev Barua |
IEEE Trans. Parallel Distributed Syst. | 1 |
| 2014 | Affine Parallelization of Loops with Run-Time Dependent Bounds from Binaries
Aparna Kotha, Kapil Anand, Timothy Creech, Khaled Elwazeer, Matthew Smithson, Rajeev Barua |
ESOP | 1 |
| 2013 | A compiler-level intermediate representation based binary analysis and rewriting systemabstractThis paper presents component techniques essential for converting executables to a high-level intermediate representation (IR) of an existing compiler. The compiler IR is then employed for three distinct applications: binary rewriting using the compiler's binary back-end, vulnerability detection using source-level symbolic execution, and source-code recovery using the compiler's C backend. Our techniques enable complex high-level transformations not possible in existing binary systems, address a major challenge of input-derived memory addresses in symbolic execution and are the first to enable recovery of a fully functional source-code. Kapil Anand, Matthew Smithson, Khaled Elwazeer, Aparna Kotha, Jim Gruen, Nathan Giles, Rajeev Barua |
EuroSys | 4 |
| 2013 | An Accurate Stack Memory Abstraction and Symbolic Analysis Framework for ExecutablesabstractThis paper makes two contributions regarding reverse engineering of executables. First, techniques are presented for recovering a precise and correct stack memory model in executables in presence of executable-specific artifacts such as indirect control transfers. Next, the enhanced memory model is employed to define a novel symbolic analysis framework for executables that can perform the same types of program analysis as source-level tools. Frameworks hitherto fail to simultaneously maintain the properties of correct representation and precise memory model and ignore memory-allocated variables while defining symbolic analysis mechanisms. Our methods do not use symbolic, relocation, or debug information, which are usually absent in deployed binaries. We describe our framework, highlighting the novel intellectual contributions of our approach, and demonstrate its efficacy and robustness by applying it to various traditional analyses, including identifying information flow vulnerabilities in five real-world programs. Kapil Anand, Khaled Elwazeer, Aparna Kotha, Matthew Smithson, Rajeev Barua, Angelos D. Keromytis |
ICSM | 3 |
| 2013 | Efficient multiprogramming for multicores with SCAFabstractAs hardware becomes increasingly parallel and the availability of scalable parallel software improves, the problem of managing multiple multithreaded applications (processes) becomes important. Malleable processes, which can vary the number of threads used as they run, enable sophisticated and flexible resource management. Although many existing applications parallelized for SMPs with parallel runtimes are in fact already malleable, deployed run-time environments provide no interface nor any strategy for intelligently allocating hardware threads or even preventing oversubscription. Work up until SCAF either depends upon profiling applications ahead of time in order to make good decisions about allocations, or does not account for process efficiency at all. This paper presents the Scheduling and Allocation with Feedback (SCAF) system, a drop-in runtime solution which supports existing malleable applications in making intelligent allocation decisions based on observed efficiency without any paradigm change, changes to semantics, program modification, offline profiling, or even recompilation. Our existing implementation can control most unmodified OpenMP applications. Other malleable threading libraries can also easily be supported with small modifications, without requiring application modification. Timothy Creech, Aparna Kotha, Rajeev Barua |
MICRO | 2 |
| 2013 | Scalable variable and data type detection in a binary rewriterabstractWe present scalable static analyses to recover variables, data types, and function prototypes from stripped x86 executables (without symbol or debug information) and obtain a functional intermediate representation (IR) for analysis and rewriting purposes. Our techniques on average run 352X faster than current techniques and still have the same precision. This enables analyzing executables as large as millions of instructions in minutes which is not possible using existing techniques. Our techniques can recover variables allocated to the floating point stack unlike current techniques. We have integrated our techniques to obtain a compiler level IR that works correctly if recompiled and produces the same output as the input executable. We demonstrate scalability, precision and correctness of our proposed techniques by evaluating them on the complete SPEC2006 benchmarks suite. Khaled Elwazeer, Kapil Anand, Aparna Kotha, Matthew Smithson, Rajeev Barua |
PLDI | 3 |
| 2011 | Retrofitting Security in COTS Software with Binary Rewriting
Pádraig O'Sullivan, Kapil Anand, Aparna Kotha, Matthew Smithson, Rajeev Barua, Angelos D. Keromytis |
SEC | 3 |
| 2010 | Automatic Parallelization in a Binary RewriterabstractToday, nearly all general-purpose computers are parallel, but nearly all software running on them is serial. However bridging this disconnect by manually rewriting source code in parallel is prohibitively expensive. Automatic parallelization technology is therefore an attractive alternative. We present a method to perform automatic parallelization in a binary rewriter. The input to the binary rewriter is the serial binary executable program and the output is a parallel binary executable. The advantages of parallelization in a binary rewriter versus a compiler include (i) compatibility with all compilers and languages, (ii) high economic feasibility from avoiding repeated compiler implementation, (iii) applicability to legacy binaries, and (iv) applicability to assembly-language programs. Adapting existing parallelizing compiler methods that work on source code to work on binary programs instead is a significant challenge. This is primarily because symbolic and array index information used in existing compiler parallelizers is not available in a binary. We show how to adapt existing parallelization methods to achieve equivalent parallelization from a binary without such information. Preliminary results using our x86 binary rewriter called Second Write on a suite of dense-matrix regular programs including the externally developed Polybench suite of benchmarks shows an average speedup of 5.1 from binary and 5.7 from source with 8 threads compared to the input serial binary on an x86 Xeon E5530 machine, and 14.7 from binary and 15.4 from source with 32 threads compared to the input serial binary on a SPARC T2. Such regular loops are an important component of scientific and multi-media workloads, and are even present to a limited extent in otherwise non-regular programs. Aparna Kotha, Kapil Anand, Matthew Smithson, Greeshma Yellareddy, Rajeev Barua |
MICRO | 1 |