This paper presents the design, simulation, and experimental evaluation of an ultrasonic data telemetry scheme with significant data rate enhancements. In the proposed idea a symbol-wise approach is employed that achieves a data rate of up to 2.2 Mbps and a symbol rate of 250 kBd. using a single 1 MHz transducer pair. As a part of the proposed scheme, an ASIC receiver circuit is proposed that introduces a baseline crossing method for efficient data recovery. The receiver circuit is designed in TSMC 180-nm CMOS technology, consumes 3.97 µW of power with a supply voltage of 1.2V and occupies a silicon area of 76 µm by 24 µm. In addition, the experimental results validate the effectiveness of the design, with a bit error rate of 7.8×10⁻⁴, providing a high-performance and power-efficient solution for ultrasonic data telemetry links.

A novel discrete-time, level-crossing analog-to-digital converter (LC-ADC) is proposed in this paper. The proposed LC-ADC exploits only one comparator for fully-differential implementation. By using a single comparator twice for each sample instead of using two separate comparators, significant area saving is achieved. The proposed DT LC-ADC is implemented using 180-nm standard CMOS technology with 8 bits of resolution, targeting a 10-kHz bandwidth. Post-layout simulation results indicate that the ADC consumes 18.94μW for a 10-kHz input signal at a supply voltage of 1.2 V. The LC-ADC achieves 11.16-bit ENOB, 68.96 dB SNDR, and 79.95 dB SFDR within the signal bandwidth, and 8.22-bit ENOB, 51.29 dB SNDR, and 55.73 dB SFDR over the full bandwidth.

This paper reports on an innovative fully-integrated exponential pulse generator. The circuit is capable of producing both rising and decaying exponential current pulses, which are digitally-programmable in time constant and peak amplitude. Intended for implantable neural stimulators, the width of generated pulses is determined using a timing pulse on the order of milliseconds. The circuit employs the exponential law of subthreshold-biased MOS transistors their gate-source voltages linearly swept using a ramp voltage. The ramp generator circuit designed for this purpose uses the difference between two digitally-programmable currents to linearly charge or discharge an on-chip capacitor. The circuit benefits from an embedded error-zeroing mechanism that compensates the destructive effect of device mismatches on the slope of the voltage ramps. This work is designed and microfabricated in a 180-nm standard CMOS process and occupies a total area of 0.022 mm2(with a total on-chip capacitance of 1.5pF). Operated under a supply voltage of 1.6V, the circuit consumes a total power of about 4.6μW.

This article reports on the design of a high-performance operational transconductance amplifier (OTA) based on a degenerative current translation and mirroring (DI-Tram) circuit. The DI-Tram serves as the core of a high-performance, bulk-driven (BD), voltage-to-current (V/I) converter. The proposed OTA features a current mode, indirect Miller compensation technique, which improves the stability and gain–bandwidth (GBW) product. Fabricated in a 180-nm CMOS process, the OTA consumes as low as 39.1 nW of power when operated using a supply voltage of ±0.2 V. The circuit achieves a GBW of 35.2 kHz, a dc gain of 75.4 dB, and a common-mode rejection ratio (CMRR) exceeding 117 dB while driving a capacitive load of$2\times 20$pF.

This paper introduces an innovative circuit scheme named 'Current TRAM,' leveraging a degenerative current steering mechanism through the implementation of three current mirrors within a closed-loop configuration. This configuration undergoes transformation into a fully differential voltage-to-current converter, demonstrating its application in the design of an integrated operational transconductance amplifier (OTA). The OTA offers a high gain-bandwidth and common-mode rejection ratio at low power. Diode-connected topologies in the current mirrors adaptively bias other transistors, eliminating the need for a common-mode feedback circuit. A common-source amplifier is employed at the output stage of the OTA to enhance the slew rate performance. Implemented in a standard 0.18 µm CMOS process with a supply voltage of 0.4 V, the proposed OTA achieves a gain-bandwidth (GBW) product of 23 kHz, a DC gain of 75 dB, and a slew rate of 15.5 V/ms. Remarkably, it accomplishes this while consuming a mere 37 nW of power and driving a capacitive load of 2 × 15 pF.

This article proposes an unsupervised online spike sorter, dedicated to brain-implantable neural recording microsystems. The main (online) spike sorting phase in the proposed approach is based on the wave shape resemblance between spike classes, realized by template matching. This phase follows an offline training phase, implemented off the implant. In the training phase, the number and centroids of the clusters are automatically determined and subsequently sent to the implant to configure the on-implant online spike sorter. Comprehensively verified using two separate datasets with a wide spectrum of spike wave shapes, the proposed approach presents average classification accuracies of$\sim 85$% (unsupervised) and$\sim 92$% (supervised). A 64-channel spike sorter was designed using a computational core with folded architecture. To make the very large-scale integration (VLSI) implementation of this spike sorter appropriate for brain implants in terms of both power and area consumption, the computations realizing the proposed approach were significantly reduced. Designed in a standard 180-nm CMOS technology, the circuit consumes$1.74~\mu \text{W}$/channel and per-channel area of 0.047 mm2. The circuit is capable of clustering neural spikes in real-time with a latency of as short as 1.36 ms. A prototype of the circuit was implemented and successfully tested.

This paper reports on the implementation of a transcutaneous capacitive wireless power transfer (C-WPT) strategy for biomedical implants. The approach is based upon a series resonant converter in which the tank capacitors are replaced with a capacitive link comprising two pairs of coated parallel plates aligned around the tissue as the dielectric material. Miniaturized printed-circuit boards are developed that incorporate all requisite circuitry on the front-side of transmitter (TX) and receiver (RX) plates, as well as 400mm2Parylene-N-coated pads on the back-side of the plates. With two 100μH inductors in series with the capacitive link, a resonance frequency of ~151kHz is measured for both series resonant tanks. The system is designed to operate above resonance at 210kHz in zero-voltage switching (ZVS) regime to minimize switch conduction losses and increase the power transfer efficiency (PTE). In experimental verification, ~ 59 to 290mW is delivered to the implant (secondary) side through 5mm-thick shoulder beef with measured PTE of >31%. A peak PTE of ~38.4% is also measured when delivering 105.5mW from a dc source of 11V on the external (primary) side.

In this paper, a new method to achieve very small current reference levels on integrated circuits with immunity to temperature variations using peaking current source with MOSFETs operating in subthreshold region is proposed. By adding a source degeneration resistor to the conventional peaking current source architecture, a zero temperature coefficient current can be generated. The proposed low-power circuit operating in the weak inversion region is designed, simulated, and fabricated in a 0.18-μm standard CMOS process. Measurement results verify the circuit operation with about 5% variation over the span of −40° C to +100° C (industrial temperature grade). The supplied current is designed to be 1.5μΑ.

This paper reports an energy-efficient waveform generator, dedicated to implantable retinal microstimulators. The circuit features flexible current-mode stimuli such as rising and falling exponential pulses in addition to rectangular pulses. In order to apply the stimulation current to the electrode at the defined current levels (±96μA) and with sufficient voltage headroom (±3V), a class AB second generation current conveyor is designed as the output stage. To upconvert the 1.2-V supply voltage to ±3.3V, the output stage is equipped with an on-chip electrode-tissue driver. Duration of the generated current pulses is programmable within the range of 100μs to 3ms. Current-steering DACs are used to set the amplitudes of pulses. They exhibit DNL and INL of 0.04 and 0.17LSB, respectively. The amplitude, duration, and time constant of exponential pulses are independently programmable. Designed in the IBM in 130nm process, the circuit consumes 1.5×1.5 mm2of silicon area. Post-layout simulation results indicate that the stimuli generator meets expected requirements when connected to electrode-tissue impedance as high as 30kΩ. The proposed design consumes a maximum of 1.2mW in the rectangular pulse mode.

This paper reports the design of a fully reconfigurable biological signal co-processor, designed to enhance processing capabilities of a generic controller proposed by the authors. The co-processor is capable of performing feature extraction on 32 channels in both time and mathematical transform domains. In the time domain, level crossings and local maxima and minima are the features the co-processor is capable of recognizing. In the transform domain, the discrete wavelet transform (DWT) is calculated using a reconfigurable DWT core. Designed and simulated in a 180-nm standard CMOS process, the co-processor dissipates a maximum power of 427 μW when calculating the DWT coefficients with 2 levels for the Daubechies3 basis function.

A novel analog-to-digital converter (ADC) architecture, named domino architecture, is introduced. The proposed idea can be taken as the continuous-time counterpart of SAR ADCs, and at the same time it resembles a series version of flash ADCs being implemented with much less circuit complexity and chip area. The basic idea is then pipelined in order to speed up the conversion process, leading in a conversion rate comparable to flash ADCs. Based on the proposed idea, an 8-bit ADC was designed in a 0.18 μm CMOS technology. The converter dissipates 21 mW at 300MS/s, 19 mW of which is dissipated by the track-and-hold blocks.

Lithographically defined microelectrode arrays now permit high-density recording and stimulation in the brain and are facilitating new insights into the organization and function of the central nervous system. They will soon allow more detailed mapping of neural structures than has ever before been possible, and capabilities for highly localized drug-delivery are being added for treating disorders such as severe epilepsy. For chronic neuroscience and neuroprosthesis applications, the arrays are being used in implantable microsystems that provide embedded signal processing and wireless data transmission to the outside world. A 64-channel microsystem amplifies the neural signals by 60 dB with a user-programmable bandwidth and an input-referred noise level of 8$\mu{\hbox{V}}_{\rm rms}$before processing the signals digitally. The channels can be scanned at a rate of 62.5 kS/s, and signals above a user-specified biphasic threshold are transmitted wirelessly to the external world at 2 Mbps. Individual channels can also be digitized and viewed externally at high resolution to examine spike waveforms. The microsystem dissipates 14.14 mW from 1.8 V and measures 1.4$\times$1.55 cm$^2$.

A new approach in sine amplitude approximation for sine-output direct digital frequency synthesizers "parabolic approximation" is presented. The proposed approximation provides an initial guess, which is much closer to the target sine amplitude than previous approximations and can be simply implemented using full-digital circuitry.