Implementation of carrier sensing-based medium access control (MAC) protocols on inexpensive reconfigurable radio platforms has proven challenging due to long and unpredictable delays associated with both signal processing on a general purpose processor (GPP) and the interface between the radio frequency (RF) front end and the GPP. This paper describes the development and implementation of a split-functionality architecture for a contention-based carrier sensing MAC, in which some of the functions reside on an field-programmable gate array (FPGA) and others reside in the GPP. We provide an FPGA-based implementation of a carrier sensing block and develop two versions of a carrier sense multiple access (CSMA) MAC protocol based upon this block. We experimentally test the performance of the resulting protocols in a multihop environment in terms of end-to-end throughput and required frame retransmissions. We cross-validate these results with a network simulator with modules modified to reflect the mean and variance of delays measured in components of the real software-defined radio system.

In this paper we present a case study of a project carried out in a telecommunications research center. The Postcards from the near Future project sought to begin to reflexively address the difficulties faced by telecommunications researchers in communicating their specialist research with colleagues and stakeholders across academia, industry and with a wider public. We devised an experimental practice based research project, Postcards from the near Future (PFTNF), as a pedagogical structure to support reflexive practical learning within the research centre to this effect. The PFTNF project invited PhD students and Post-Doctorate researchers within the telecommunications research lab to express their technical research through making postcards. The postcards created visual and narrative fictions of a future where research carried out within the telecoms lab might actually become deployed. Our case study of the PFTNF project provides insights into the nature of the challenge of communicating complex technical research. We show how the experimental communicative practice developed through the PFTNF project influenced researchers and catalyzed change in the communicative culture of the telecommunications lab. We argue that the kind of experimental communicative practice engendered within the PFTNF project merits further research and development, and we make suggestions to this effect.

The promise of 24/7 patient monitoring and online diagnosis using wearable and implantable biomedical devices has engendered significant research interest in the development of low power biosignal processing platforms. A novel Coarse Grained Reconfigurable Array (CGRA) architecture is presented for low power, real time processing of biomedical signals. The proposed architecture differs from previously proposed CGRAs in that it is designed for low power, rather than for high performance. The proposed architecture was implemented in a software modeler and simulator and in Verilog. The architecture was shown to provide average savings in energy consumption of 62% compared to conventional DSP and SIMD processors and average speed ups of 30× and 8×, respectively, for typical biosignal processing algorithms.

Googlepsilas PageRank (PR) eigenvector problem is the worldpsilas largest matrix calculation. The algorithm is dominated by Sparse Matrix by Vector Multiplication (SMVM) where the matrix is very sparse, unsymmetrical and unstructured. The computation presents a serious challenge to general-purpose processors (GPP) and the result is a very lengthy computation time. In this paper, we present an architecture for solving the PR eigenvalue problem on the Virtex 5 FPGA. The architecture is optimised to take advantage of the unique features of the PR algorithm and FPGA technology. Performance benchmarks are presented for a selection of real Internet link matrices. Finally these results are compared with equivalent GPP implementations of the PR algorithm.

Sparse matrix by vector multiplication (SMV) is a key operation of many scientific and engineering applications. Field Programmable Gate Arrays (FPGAs) have the potential to significantly improve the performance of computationally intensive applications which are dominated by SMV. A shortcoming of most existing FPGA SMV implementations is that they use on-chip Block RAM or external SRAM to store the matrix, which severely limits the problem size. Real applications, such as Finite Element Analysis (FEA), require large memories. Realistically this capacity can only be provided by commodity DRAM. In this paper we address the problem of SMV for large matrices using commodity memory. We implement SPAR, a special purpose architecture that was previously proposed for large SMV computations in a VLSI co-processor using cheap external memory. We present an empirical evaluation of the SPAR architecture for use on FPGAs and highlight challenges that arise when tackling realistic FEA problems.